VLSI architecture for Vasanth sorting to denoise image with minimum comparators

Highlights

• A novel sorting technique called Vasanth sorting is proposed using 25 comparisons to sort 9 numbers in increasing order.

• A novel parallel VLSI architecture for Vasanth sorting was also formulated.

• The parallel VLSI architecture was targetted for Virtex and Virtex 7 devices and results were tabulated in terms of area, speed, power.

• The proposed parallel VLSI architecture for Vasanth sorting was compared with standard sorting techniques and found to be area efficient and works at high speed when compared to existing sorting algorithms.

Abstract

An efficient VLSI architecture for minimized sorting network (Vasanth sorting) in rank ordering application to remove salt and pepper noise is proposed. The basic operation in salt and pepper noise removal is rank ordering. In this work, a novel 2D sorting technique referred to as Vasanth sorting is proposed for a fixed 3 × 3 window. Vasanth sorting requires only 25 comparators to sort 9 elements of the window. A parallel architecture is developed for Vasanth sorting with 25 comparators. The processing element of the parallel architecture is an 8-bit data comparator (Two cell comparator). The performance of the proposed sorting technique is compared with the different sorting technique which is targeted for XCV1000-5bg560 on XILINX 7.1i and xc7v2000t-2flg1925 Xilinx 14.7 project manager respectively with Modelsim 10.4a for simulation and XST compiler tool for synthesis using VHDL. It was found that the parallel architecture developed for Vasanth sorting requires the only ¼ of the area in FPGA when compared to existing sorting techniques. The combinational delay of the proposed architecture was also twice as less like their counterparts. The power consumption of the logic was 7mw. Hence the above performances make Vasanth sorting a better choice compared to existing techniques for rank ordering.

Introduction

Rank order filters are non-linear filters widely used in applications like smoothing, noise reduction, edge detection, image enhancement, and classification but we mainly focus only on image de-noising. The main operation of the median is rank ordering technique. Rank ordering is done by sorting mechanism in order to reduce the number of comparators and the basic operation involves in sorting is arranging the list of data in increasing among the data items. Over the years many researchers have developed VLSI architectures targeting reduced area, high speed, and low power. Rajasekhar et al. [1] developed a new design of comparator using Full adder which is the basic building block of ALU and the objective is to realize the design of low power and reduced area of a conventional 16-bit comparator using a new style 2-bit comparator for 0.12um technology. Patel et al. [2] developed a comparator were developed using different styles of full adder by means of DSCH and Micro wind tool using 120 and 70 nm technology. Anjuli and Anand [3] proposed a 2-bit magnitude comparator with special logic styles and comparison of these designs is simulated using 90 nm technology with Tanner EDA tool. Rangaraju et al. [4] developed a reversible binary comparator and the design depends on properties of PG (Peres Gate) gate which is appropriate for a comparator. The first stage of the design is n-bit reversible binary comparator as an input circuit and the second stage is 1-bit comparator cell and so on. It was found that the Garbage output and Quantum cost Garbage output values are less compared to existing techniques. Sinha and Tripathi [5] developed a BDD based optimization of a 4-bit magnitude comparator circuit, also compared results of BDD and pre-computation strategy that leads to improvement in power. Nodes and Gallagher [6] proposed the distribution of the output of the median filter using 1-D and the resultant intended for numerous cases together with the kth-order output along with an input distribution. Shrestha [7] compared different image de-noising methods and a new method was developed using decision-based for impulse noise removal and the simulation is done by using MATLAB. The proposed new technique gives better performance compared to existing methods and the performance of the algorithm flatters at high noise densities. Teoh et al. [8] studied the present development on Median Filtering techniques which are utilizing in Digital Grayscale Image Processing and these new methods of the median filter are based on only online literature available. Pang et al. [9] proposed a new adaptive median filter named as Adaptive Partition-Cluster-Based Median (APCM) Filter for the purpose of removal of random-valued impulse noise in images. These filter can suppress the noise and as well as it preserves the image. The advantage of the proposed method is it does not involve loop iterations so simple structure and low computation complexity which leads to much responsive to hardware parallel implementation of image processing. Teoh and Ibrahim [10] conducted a literature survey on eight well known Median Filtering Frameworks and also include advantages and disadvantages of these frameworks for the reduction of Impulse Noise from Grayscale Digital Images. Gupta [11] developed a new algorithm and it is based on the principle of efficient noise detection in corrupted images. The proposed filter uses the impulse noise detector and it is based on an order statistic filter. The main advantage of this algorithm for the removal of noise range from 10% to 98% and it also preserve the edges with high quality and also a comparison of the median, mean and improved median filter. Szanto and Feher [12] developed numerous algorithms and it can be used on parallel architectures. The Histogram-based algorithm is proposed that can be executed on GPUs, which results in a fast algorithm for medium-sized filter windows and an implementation of optimized sorting network is introduced for smaller filter window sizes. Abirami [13] introduced an implementation of Merge Sort Algorithm with VHDL. Devi et al. [14] introduced a VLSI design of high-speed search algorithm to implement enhanced Diamond Search of Block-based Motion estimation for video compression systems. This algorithm mainly reduces search points and a new Motion Estimation algorithm to help optimized VLSI implementation with well-organized comparators and compressors. The main advantage of the proposed architecture exhibits low power and high speed with no changes in the video quality. Farmahini-Farahani et al. [15] designed a low latency and high throughput sorting techniques and the architecture is designed with modular methods, pipelined and parameterized. The proposed iterative sorting used a small sorting unit in order to determine the biggest values. Chen and Viktor [16] introduced the hardware generator that automatically generates architectures of sorting on FPGA. RAM structure is based on a vertically folding standard network is proposed and the main advantage is the improvement in energy and memory of the proposed designs respectively. Alnihoud and Mansi [17] developed an enhanced bubble and enhanced selection sorting algorithms with complexity O (n log n) instead of O (n²) for bubble and selection sort algorithms. The proposed algorithms are efficient compared to shell sort and enhanced shell sort because it increases the efficiency of algorithms. Prajapati et al. [18] compares different types of sorting algorithms based on their parameters and also give their advantages and disadvantages along with applications. Verma and Kumar [19] introduced a new sorting algorithm called list sort which is based on dynamic memory allocation. Due to this dynamic nature, it is fast compared to conventional sorting algorithms. The main advantage of this sort is, it is already sorted in ascending or descending order. Pathak et al. [20] developed a very fast sorting algorithm with efficient memory which is used for sorting the list of data. The proposed paper studied some different types of sorting techniques and comparison of a set of data based on their time complexities. Vega-Rodriguez et al. [21] proposed the architecture using parallelism techniques called replication and pipelining for the implementation of a median filter with FPGA. The optimization done in proposed architecture leads to meet real-time processing with the least amount of resources. The main advantage of the proposed method is it uses the only small number of exchange network necessary in order to find the median. Zhang and Zheng [22] developed a fixed sorter to sort the larger set of inputs by using a new parallel sorting algorithm and also introduced VLSI architecture of these new sorting algorithm with MM-sorter based on MM-sorting. The advantage of this sorter is its performance is well designed for random inputs and well fit for VLSI realization. Roncella et al. [23] introduced the implementation of new design with parallel VLSI architecture for two-dimensional rank order filter using CMOS technology based on the operation of median finding. The advantage of this architecture it is possible to push the pipeline level to bit level without any change. Vasanth et al. [24] proposed a VLSI architecture for a finite state machine using a filter called unsymmetrical trimmed midpoint for removing salt and pepper noise in images. The developed parallel architecture for sorting requires less amount of area and also an improvement in speed and power compared to existing sorting algorithms. Vasanth and Karthik [25] introduced an algorithm and its FPGA implementation for a 3 × 3 median filter window and the concept of this algorithm is based on the implementation of 9-bit optimized sorting network using VHDL. The main advantage of this sorting network is high operating speed and lesser hardware complexity. Over the years a need for faster sorting technique is required in many image applications such as noise removal, classifications etc., but the number of comparators requires hampers its speed. The need for a well-organized sorting network is essential for any rank ordering applications especially rank ordering. Hence a suitable sorting technique has to be formulated with a reduced comparison. The VLSI architectures developed for sorting either lacks speed or consumes more area and power. A VLSI Architecture which consumes less area, operates at high speed and consumes less power has to be formulated. Section 2 illustrates the Vasanth sorting. Section 3 gives the parallel architecture for Vasanth sorting. Section 4 gives discussions and simulation results and finally table comparing all the sorting techniques. Section 5 gives the conclusion of the work.