Reversible logic-based magnitude comparator (RMC) circuit using modified-GDI technique for motion detection applications in image processing

Abstract

Reversible or information lossless gates have applications in nano-technology, digital signal processing (DSP), communication, computer graphics and cryptography. Gate-diffusion input (GDI) technique can provide the possibility of designing fundamental gates in ultra-low power and layout chip area with low number of transistors. A reversible logic-based single-bit magnitude comparator (RMC) circuit is presented by using the modified-GDI (m-GDI) method-based reversible gates for designing RMC in any arbitrary number of bit levels for processing at nano-scales.

In this paper, several figure of merits (FOMs) like: energy consumption-propagation delay product (EDP) and worst delay-power consumption-chip area product (DPA) are evaluated and compared with other designs. The simulation results show the improvement of the evaluation parameters of the proposed RMC in compare with the other similar basic GDI-based comparators. Also, according to the simulation results, presented comparator is capable to work at extensive frequency ranges with higher maximum operating frequency (f_max.). The effects of different process, voltage and the temperature (PVT) variations are extensively evaluated by Monte-Carlo simulation. According to the results, the proposed circuit is robust against PVT variations and also noise-tolerable parameter.

Moreover, the proposed RMC architecture is used in images applications. The results show that output images of the proposed inexact RMC have a very high quality and resemblance to the images generated by exact RMC, thus excellent values for the peak signal-to-noise ratio (PSNR) and mean structural similarity index metric (MSSIM) indicate that the proposed inexact RMC circuit has a proper accuracy for applications such as: comparative analysis in medical images, motion detector, edge detection and segmentation in nano-technology. Therefore, using the proposed scheme can be improved in comparator circuit in chips for future generation of VLSI and ULSI blocks, like: nano-processors performance.

Introduction

One of the best approaches for designing future computers is using reversible logic. Reversible logic has emerged as a promising paradigm in various domains, such as ultra-low power very-large-scale integration (VLSI) and ultra-LSI (ULSI) design, quantum cellular automata (QCA), and nano-technology-based systems. Since no information is lost in reversible circuits, so no heat produced and energy is not released. Consequently, the internal power consumption is lower and optimized in reversible circuits in compare to combinational types in the conventional complementary metal–oxide–semiconductor (CMOS) logic [1], [2]. Ref. [3] showed that the energy dissipation which is equal to kT × (ln 2) joules of energy, where k is Boltzmann's constant and T is the temperature, for each bit of information in circuits [4], energy can be stored by implementation and designing circuits in reversible logic. Combinational gates in conventional CMOS logic dissipate heat for every bit of information that is lost during their operation. Due to this fact the information once lost cannot be recovered in any way. But the same circuit if it is constructed using the gates in reversible logic will allow the recovery of the information.

The standard MOSFET-like carbon nanotube-based field-effect transistors (CNTFETs) have been used in order to achieve the lower power consumption, lower values of intrinsic (parasitic) capacitances, smaller size (nano-scale) and scalability, ballistic transfer and higher mobility of carriers for improving the performance of logic circuits. Another important benefit of using CNTFET technology includes the similar values of carrier mobility for both N-type and P-type CNTFET devices (μ_n = μ_p) with the same transistor dimensions that leads to an identical driving capability and current-voltage (I-V) characteristics as compared with conventional silicon-metal oxide-semiconductor field-effect transistors (Si-MOSFETs) [5]. Reversible logic gates are designed to reduce transistor count, area and power dissipation of digital (or binary) comparator circuit. Comparator circuits are very important and they are commonly used for computing systems like: analog-to-digital and digital-to-analog convertors (ADCs and DACs), error detectors, communications systems, signal processing architectures [6], [7], central processing units (CPUs) and microcontrollers (MCUs). As magnitude comparator (MC) is very basic arithmetic unit, to cope up with high speed and optimum power for big data analytics, we need suitable MC architecture. Nowadays the implementation and designing of a reversible logic-based magnitude comparator (RMC) with high calculation capacity and low power is very essential for designers [8]. Today's electronics world is competing with ultra-low power and less chip area of digital combinatorial circuits. Gate-diffusion input (GDI) method [9] with simple cellular structure has been proposed in order to reduce the power dissipation, chip area and complexity in the designing of fundamental logic gates. A digital or MC is an electronic hardware device that takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to the other number. This paper presents the design of a new energy-efficient single or one-bit RMC using reversible gates based on the modified-GDI (m-GDI) method with the help of useful properties of CNTFET technology [10], which has high capacity and ultra-low power, chip area and complexity in nano-process. After that, the advantages of the efficient performance of the m-GDI method in designing the MVL-based logic gates for image processing applications [11], the dual-modulus frequency prescaler (DMFP) circuits [12] and ultra-efficient analogue and logical blocks in voltage-mode fuzzy and quantum systems [13], flip-flops circuits [14] and low-power, high write/read stability static binary (two-valued) and ternary (three-valued) memory cells in nano-process [10], [15], [16] are presented. In addition, the evaluation parameters of the other designed circuits based on m-GDI cell can be optimized with algorithms [15], [17].

This paper presents the design of a new energy-efficient the single-bit RMC circuit based on the m-GDI method in 32 nm CNTFET technology. The main purpose of this design is to introduce a new circuit topology plus a technology migration from CMOS to CNTFET in order to maximize the advantages of gate circuits in reversible logic and GDI technique. Therefore, the proper combination of these two benefits results in an improved overall performance of the proposed structure for application in future generation of VLSI and ULSI chips. A reversible logic-based single-bit RMC circuit is presented in nano-process with the help of useful properties of standard reversible Fredkin and M gates [18], [19] implemented based on m-GDI method for designing RMC in any arbitrary number of bit levels for processing at nano-scales. The simulation is done in 32 nm technology with Synopsys H-SPICE simulator under the condition of different supply voltage, maximum operative frequency and room temperature. The simulation results show that the proposed RMC circuit has an improved evaluation in term of several figure of merits (FOMs) like: energy consumption-propagation delay product (EDP) and worst delay-power consumption-chip area product (DPA) parameters in compare with RMC circuit with basic GDI method [19], [20] and the conventional reversible binary comparator [21].

The impact of process, voltage and temperature (PVT) variations are analyzed with Monte-Carlo simulation. The results show that the implementation of the proposed RMC circuit based on m-GDI method with different chirality vectors dramatically reduces the power consumption, sensitivity to process with substantial small standard deviation and better noise-tolerable compared to other state-of-the art designs in same technology.

Also the proposed single-bit RMC circuit is applied in digital image processing. The results show that the proposed inexact (approximate) RMC provides excellent capabilities to accomplish comparison on the image with respect to peak signal-to-noise ratio (PSNR) and mean structural similarity index metric (MSSIM) more than 50 dB and 0.99, respectively, thus it is totally acceptable for most similar applications. At the end, the proposed comparator structure can be used to block design of the internal circuits such as: ADC in order to implement the applied algorithms to the image processing like: comparative analysis in medical images, motion detector, edge detection and segmentation in nano-scale.

The paper is organized as follows: a brief review of CNTFET structure and the background on the m-GDI method are studied in Sections 2 and 3, respectively. Review of reversible logic and gates in this logic, also the proposed single-bit RMC circuit based on m-GDI method are presented in Sections 4 and 5, respectively. The simulation results are provided in Section 6 and finally the whole work is concluded in Section 7.