A novel majority based imprecise 4:2 compressor with respect to the current and future VLSI industry

Abstract

Imprecising the arithmetic hardware blocks is well known as one of the brilliant approaches that increase the performance of digital signal processors (DSP) at the cost of imposing some acceptable errors. Making a trade-off between the performance and the enormous results of a given system is a challenge which has attracted the interest of many researchers in recent years. In this paper, we focus on the design of an imprecise 4:2 compressor which lies at the heart of inexact multipliers. The proposed imprecise 4:2 compressor by utilizing only one majority gate brings significant efficiency in implementation of today's technologies like FinFET and future majority based emerging technologies such as QCA. The evaluation results in both of aforesaid technologies demonstrate the remarkable improvement of the proposed design compared to related works. In addition, employing the proposed imprecise 4:2 compressor in an image processing application confirms the qualitative acceptability of the proposed design.

Introduction

High accuracy and reliability are important features in the semiconductor industry which are involved in designing computing structures beside efficiency in performance and power consumption [1]. Embedded digital arithmetic blocks in these devices are also not excluded from the above-mentioned facts [2]. Nonetheless, many applications can sustain errors and non-accurate computation and yet the results are good enough to use. Multimedia applications like image processing are examples of a suitable case to utilize imprecise algorithms and structures [3]. During recent decades, the market of electronic portable devices has witnessed tremendous growth [4]. In portable devices, the source of energy is provided by a limited battery. Therefore, energy efficiency turns into one of the biggest concerns in the design of electronic portable devices [5]. Multimedia processing takes the lion's share of the overall processes in electronic portable devices. Applying imprecise computing methods in such applications bring advantages, including decreasing the hardware complexity, reducing the power dissipation as well as enhancing the performance [6], [7]. Digital signal processors (DSPs) offer brilliant computing platforms for multimedia processing due to their superior performance, high levels of integration and low-power consumption [8]. As a matter of fact, arithmetic circuits are the major blocks of DSP and multiplier is one of the foremost, frequently used and critical arithmetic blocks. Therefore, enhancing the performance and energy-efficiency of multiplier block has a significant impact on the performance of the electronic portable devices. Multiplication is composed of three steps: in the first step, the partial products are generated from "multiplicand" and "multiplier. In the second step, the partial products are reduced to only two operands in a carry-free structure. Finally, in the third step, a fast addition is conducted to yield the final result. Among these steps, the second one utilizes the most chip area, consumes a large amount of power and contributes to the maximum propagation delay compared to the rest of the blocks [9]. The partial product reduction techniques such as Wallace and Dadda suffer from VLSI irregularity due to using only full and half adders [2]. Compressors can be utilized instead of full adders in order to enhance the circuit regularity and reducing the latency as well as the power consumption of the partial product reduction stage. 4:2 compressor structures are preferred to other compressor degrees, due to lower complexity as well as premier regularization [10]. Therefore, designing an efficient 4:2 compressor has attracted much more attention from researchers. This led to several contributions in the literature, considering the critical path, area and power consumption reduction of this vital arithmetic block. These contributions, comprise the design of 4:2 compressor both in precise and imprecise structures in a variety of technologies [9], [10], [11], [12], [13], [14], [15], [16]. In this paper, we also introduce a novel circuit for imprecise 4:2 compressor design. Similar to [16], for the realization of the proposed imprecise 4:2 compressor, two well-known devises in the nano era are considered. FinFET as the prevailing technology of today's industry with significant features such as smaller drain induced barrier lowering (DIBL), smaller subthreshold swing, and higher I_on/I_off [17], [18], and Quantum-dot Cellular Automata (QCA) as an emerging technology with promising features like ultra-high density, very low power consumption, and significant switching speed for future VLSI industry [19], [20]. The underlying idea behind all realization is the adoption of more simplified logic expression considering the VLSI features of the aforesaid technologies. The proposed design results in a significant saving in terms of area occupation, power dissipation as well as propagation delay in both targeted technology.

The rest of this paper is organized as follows. In Section 2, a review of the related works is conducted. In Section 3, a logical description of the proposed imprecise 4:2 compressor is presented based on the majority gate. The VLSI realization of the proposed 4:2 compressor is also detailed for both FinFET and QCA technologies. In Section 4, the performance of the proposed 4:2 compressor is evaluated against the related state-of-the-art. For this purpose, for each technology, its specific performance criteria are considered. In addition, as in the design of imprecise structures, the compromises between the output error and other performance criteria are considered. As a case study, the application of image processing based on the multipliers with imprecise compressors is considered. Finally, Section 5 concludes the paper.