Design and analysis of CMOS RF receiver front-end of LNA for wireless applications
Introduction
Low Noise Amplifier (LNA) for radio frequency (RF) device is worn into every sole thing. For example, radios astronomy, cell phones, Wi-Fi, and wireless LANs were cover 2.4 GHz frequency range are quickly famous in the present scenario [1]. The different standards of communication [2] use different techniques of modulation and are at different operating frequencies. Radio frequency manufacturing has taken a harsh revolutionize since the days of Marchese Marconi [3] who developed the radio transceiver communication. The LNA block is one of the foremost blocks in all types of system receivers. The signals that come from an antenna are comparatively weak like few μV or nV range of the signal. Therefore it needs necessary to amplify the signal using LNA to improve the signal strength shown in Fig. 1 [4].
The basic building block of radio frequency (RF) front-end architecture illustrates in Fig. 1 [5], [6]. Fundamentally, front-ends are liable for tracking feeble signals at high frequency range and through mixer which is translating into IF signal for further section with prominent power range.
For wireless receivers the LNA is an interface between the antenna terminal and the digital modem. Therefore, it desires better-performance of analog circuits like LNA, mixer and oscillator. The leading challenge of LNA circuit is to provide a high gain along with a low noise figure [7]. The IEEE 802.15.4 standard uses 3 major frequency spectrum bands with license-free [8], [7]. They are 860MHz, 920MHz, and 2.4GHz between these bands of frequency spectrum 2.4GHz [9], [10] is being utilized globally. The ultra-wideband, commonly known as UWB, is a band of frequency with more data transmission rate. The Federal Communications Commission (FCC) [11] recommends 3–10 GHz as communication links.
The key challenge of low noise amplifier is to offer improved performance with less NF, high gain, and sufficient linearity [12]. The main objective of this paper is to design the LNA of single-stage and two-stage amplifier to improve the high gain, less noise figure, better reverse isolation, and improved linearity [11].
Section snippets
Design and analysis of proposed LNA
The fundamental design steps helps to the flow of RF front-end of LNA it is illustrated in Fig. 2 [4]. According to specifications of RF front-end receiver, wireless standards and LNA the important parameter and component values are easily determined. In order to maintain input-output matching network, the preferred topology can be chosen. If design specifications are met with analysis, then the circuit can be designed and verified with the simulated results.
LNA design and results discussion
The LNAs major function is to afford enough gain to conquer the noise of the subsequently stages. Where, the receiver's sensitivity generally depends on the LNAs gain and noise figure. In this effort the LNA amplification block is modified for enhanced noise figure and gain. Based on this standard the two innovative LNA structures are realized as single-stage and cascaded stage topologies. The proposed schematic of single-stage and two-stage LNA is illustrated in Figs. 8 and 9 [11].
The signal
Conclusion
The field of wireless receiver communications has undergone enormous growth, moving quickly during a sequence of generations in the present scenario. The receiver design with low noise is a foremost design constraint. For this context, the design of the LNA for better performance is of immense importance. The proposed LNA for radio frequency front-end is designed with very little NF and high gain using 45nanometer in cadence virtuoso tool and simulate the results by using SpectreRF simulator.
Ethical approval
This article does not contain any studies with human participants or animals performed by any of the authors.
Declaration of Competing Interest
This paper has not communicated anywhere till this moment, now only it is communicated to your esteemed journal for the publication with the knowledge of all co-authors.
Mahesh Mudavath was born in Warangal, Telangana state, India. He received the B.Tech degree in Electronics and Communication Engineering from JNTU Hyderabad, India. He received M.Tech degree in VLSI Design from C-DAC Mohali, Chandigarh, India. Presently he is pursuing the Ph.D. degree in the area of VLSI Design from K.L.E.F (Deemed to be University), Guntur, India. His research interests include CMOS analog circuits, RF wireless transceiver design, and Low Noise Amplifier Design. He is a life
References (21)
- et al.
Analysis and design of moderate inversion based low power low-noise amplifier
IET Comput. Digit. Tech.
(2016) VLSI for Wireless Communications
(2011)CMOS RF Receiver Design for Wireless LAN Applications
(1999)- et al.
Differential CMOS low noise amplifier design for wireless receivers
Int. J. Recent Technol. Eng.
(2019) RF Microelectronics
(1998)CMOS technology characterization for analog and RF design
IEEE J. Solid-State Circt.
(1999)- et al.
Linearization of low noise amplifier for wireless sensor networks
- et al.
Design of CMOS RF front-end of low noise amplifier for LTE system applications
Asian J. Inf. Technol. Medwell J.
(2016) CMOS RF receiver design for wireless LAN applications
A 2.4-GHz CMOS receiver for IEEE 802.11 Wireless LAN's
IEEE J. Solid-State Circt.
(1999)
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Mahesh Mudavath was born in Warangal, Telangana state, India. He received the B.Tech degree in Electronics and Communication Engineering from JNTU Hyderabad, India. He received M.Tech degree in VLSI Design from C-DAC Mohali, Chandigarh, India. Presently he is pursuing the Ph.D. degree in the area of VLSI Design from K.L.E.F (Deemed to be University), Guntur, India. His research interests include CMOS analog circuits, RF wireless transceiver design, and Low Noise Amplifier Design. He is a life member of ISTE.
Hari Kishore Kakarla was born in Vijayawada, Andhra Pradesh, India. He received B.Tech in Electronics & Communication Engineering from JNTU, Hyderabad, India and M.Tech from SKD University, Andhra Pradesh, India. He completed the Ph.D in the area of VLSI from K L University, Guntur, Andhra Pradesh, India. Presently he is working as Professor in ECE, K.L.E.F (Deemed to be University), Guntur, Andhra Pradesh, India, where he has been engaged in teaching, research and development of Digital Testing, Low-Power VLSI, High-Speed CMOS VLSI, System on Chip, Memory Processors, ASIC Fault Testing, Embedded Systems, and Nanotechnology. He has published 75 International Journals, 02 IEEE Transactions, 04 Patents Filled and Published. He is a life member of MISTE, AMIE, MIACSIT and MIAENG.
Azham Hussain is the Associate Professor of Software Engineering at School of Computing, Universiti Utara Malaysia, Kedah, Malaysia. He is the founder of Human-Centered Computing Research Group, which is affiliated with the Software Technology Research Platform Center at School of Computing, Universiti Utara Malaysia. Azham Hussain is a member of the US-based Institute of Electrical and Electronic Engineers (IEEE), and actively involved in both IEEE Communications and IEEE Computer societies.
Boopathi C.S has completed his BE in electrical & electronics engineering, M.E in Power systems and PhD in Electrical engineering. He has published 32 papers in international journals. His areas of interest are ANN, wireless networks. He is currently working as associate professor in the department of electrical and electronics engineering, SRM institute of science and technology, Chennai, India.
“This work was supported in part by the VLSI design laboratory, central institute of tool design (CITD), Balanagar: Hyderabad. And also institution of Vaagdevi College of Engineering, Warangal (T.S), India, for financial support.”