FPGA-based variable modulation-indexed-SPWM generator architecture for constant-output-voltage inverter applications

Abstract

Modulation Index (MI) variant sinusoidal-pulse-width-modulation (SPWM) is desirable for converter applications in maintaining output voltage under variable input and load environments. Enabling a high-speed switching and resolution, field-programmable gate-arrays (FPGAs) have been dominating in digital control of power electronics. This paper proposes an FPGA-based high-frequency high-resolution digital variable-modulation-indexed sinusoidal-pulse-width-modulation (DVMI-SPWM) generator architecture which can support the requirements of modern high-frequency switching and the MI adjustment ability in voltage-source-inverter (VSI) applications. A mathematically formulated optimized finite-state-machine (FSM) architecture is introduced, which adopts MI of SPWM by adjusting the duty-cycle values of SPWM pulses based on the measured feedback signal. The design employs a minor segment of medium-sized FPGA and, thereby, provides a good trade-off for multi-functional and larger schemes. The post-design simulation and experimental results validate that compared to the earlier-reported architectures, the proposed DVMI-SPWM architecture is the most appropriate one for variable MI applications with improved performance such as lower power consumption, lower harmonic distortion, and higher resolution.

Introduction

POWER-electronic switches are the main concern in the design of power converters for many applications like dc/ac inverters [1], variable speed drives and uninterrupted power supply (UPS) [2], etc. In such applications, the switching technique for power-electronic devices has an important role in shaping the desired output. Different types of switching techniques are in practice. Among them, sinusoidal-pulse-width-modulation (SPWM) technique is a common one for the purpose where dc to sinusoidal ac output is obligatory. The reduction of harmonics from the inverter output voltage is the prime benefit of using SPWM switching of the power-electronic devices (e.g., MOSFETs, IGBTs, etc.) in the inverter [3,4]. An inverter is generally intended to function at triggering frequencies in the range of 1–100 kHz, depending on power rating and application [5], [6], [7]. The size and cost of an inverter output filter can be reduced by increasing the switching frequency ( f_sw) of the semiconductor devices in the inverter [8]. A single-phase inverter comprised of four semiconductor switches has a good trade-off between efficiency, complexity, and cost [9]. A simplified block diagram of such an inverter is depicted in Fig. 1, where; a load variation causes a deviation in inverter output voltage (ΔV), which in turn changes the Modulation Index value (Δm) i.e., the Modulation Index is adjusted to minimize the inverter output voltage variation. An FPGA controller is used to generate the requisite SPWM switching signals for the semiconductor switches, driven through the gate drivers. A low-pass inductor-capacitor (LC) or inductor-capacitor-inductor (LCL) type filter is used for mitigating the high-frequency harmonics from the bridge output $V_{dvmi-spwm}$ [9] while achieving a low-frequency sinusoidal waveform ( V₀) at the inverter output. The amplitude of  V₀ is related as:

$$V_0=m{V}_{DC}=\frac{V_c}{V_{tr}}·V_{DC}$$

where, V_DC is the dc input voltage of the inverter;  V_c and  V_tr define the voltage amplitudes of the reference sine and carrier signals, respectively, in the SPWM generation; m is the Modulation Index (MI) of the SPWM. The trend of increased switching frequency is likely to be prolonged while incorporating the latest advancements of high-speed power switches, built with Silicon-Carbide, Gallium-Nitride, etc. [10,11]. These switches are competent enough to operate at a higher switching frequency range (up to 3 MHz) with lower power losses [12].

With the advent of several digital technologies like microcontrollers, digital signal processors (DSPs) and field-programmable gate-arrays (FPGAs), there has been an increased interest to generate custom-made SPWM for different power electronics applications. In digital carrier-reference based SPWM architecture, an up-down counter is configured to realize a triangular carrier wave, and a lookup table (LUT) is utilized to accumulate the digital samples of a reference sine-wave [12], [13], [14]. A direct digital synthesis (DDS) technique, based on the evaluation of a sinusoid and a triangular signal using a high-speed comparator, is also reported in [15,16]. In [17], a novel digital SPWM generation technique has been developed and implemented in dsPIC which calculates the duty-cycle count values of pulse-train with the high-speed Harvard architecture. A DSP implementation of carrier-based pulse-width-modulation (PWM) technique is presented in [18], which is aimed to reduce the common-mode voltage of a three-level four-leg converter. Bowes and Holliday [19] have proposed a regular-sampled PWM technique aimed to rationalize the computation time in order to obtain higher switching frequency, where a set of pulse-widths is to be calculated once and used over a finite number of consecutive switching edges of the SPWM pulse train. The timing-cycle of hardware timer with the microprocessor and DSP-based implementation imposes a limitation on time resolution of duty-cycles of SPWM pulses [20]. Thus, most of the earlier SPWM generations are restricted within a limited switching frequency band (i.e., up to10 kHz).

FPGA is more preferable than microprocessor and DSP due to higher execution speed, parallel processing facility, and easiness in hardware integrity. Thus, FPGA based inverter control logic implementations have extensively emerged during the last few years [21]. Coordinate rotation digital computer (CORDIC) algorithm has been proposed to generate sinusoidal wave aimed at reducing memory requirement in FPGA-based implementation [22]. Though the hardware multiplier is avoided in this architecture, the execution speed of the algorithm is not high enough compared to the LUT based one.

In order to increase the switching frequency range (up to 1 MHz), Lakka et al. [23] have used a high-speed SPWM generation architecture using XC5VLX110T Virtex-5FPGA device. But, the application of this architecture is restricted to stand-alone inverters only. In recent years, some FPGA-based radical modulation schemes have been designed for adopting more improved switching and control strategy for inverter applications [24,25]. Stellato et al. [25] have reported an FPGA-based dynamic modulation technique for reducing computational burden at lower sampling times (below 25 μs) while generating switching pulses of a three-phase VSI. The direct model predictive modulation technique employs a large segment of the FPGA device. Hence, the control scheme is not suitable for higher Modulation Index and high switching frequency application in modern dc/ac power converter. Another FPGA-based timing correction algorithm for reducing power consumption of SPWM generator has been proposed in [26], which is implemented in a neutral-point clamped inverter-fed ac drive. Though the percentage of Total Harmonic Distortion (THD%) of the inverter output voltage is lower than that of [23], but the application of this architecture is also restricted to the stand-alone inverters only. Recently, a mathematical analysis of digital SPWM for single phase full-bridge VSI using a uniform multi-sampled technique has been reported in [27]. Though, the time domain analysis presented in this paper, establishes a relation between the fundamental, carrier, and sampling frequencies; the implementation is limited to a lower switching frequency range (i.e., up to 10 kHz). A spread spectrum frequency modulation technique for digital SPWM generation along with electromagnetic interference (EMI) mitigation property is presented in [28]. Two FPGA-based space vector pulse-width-modulation (SVPWM) generation algorithms (2D-SVPWM and 3D-SVPWM) are reported in [29], with a comparative analysis of their performance. But, none of the above FPGA-based architectures is found to be suitable with the MI variation ability in SPWM generation. Therefore, an advanced SPWM generation architecture for supporting the features of high-frequency switching and MI variation is highly essential in the instrumentation of the VSI to be adapted under variable input and load conditions.

This paper presents an FPGA-based digital variable-modulation-indexed sinusoidal-pulse-width-modulation (DVMI-SPWM) generator architecture which is proficient to generate high-frequency SPWM along with MI adjustment ability. Thus, the proposed architecture is favorable in designing the control/switching circuitry for a VSI where a constant output voltage under variable input and load environment is required. In the proposed FPGA design, the pulse generation section is sub-divided into two units in such a way that the digital values of the positive half-cycle of sinusoidal wave are counted in one unit and for the negative half-cycle are counted in the other unit. The duty-cycle values of pulses are transformed into new values while updating the Modulation Index value of SPWM in accordance with the external feedback signal from the inverter output. An optimized finite-state-machine (FSM) structure is designed for realizing a pre-formulated mathematical equation. Furthermore, the proposed FPGA-based design can be enabled to define or change the initial value of MI at any time throughout the execution of the algorithm.

The rest of the paper is structured as follows. Section 2 describes the proposed FPGA-based DVMI-SPWM generator architecture in detail. Section 3 explores the validation of the proposed architecture with the presentation of simulation and experimental results. Finally, performance comparisons amongst the various SPWM generation architectures under study are presented in Section IV, followed by the conclusion in Section 5.