Sample preparation techniques for physical analysis of VLSIs

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Abstract

A sample preparation machine introduces a variety of techniques for low-damage sample preparation, especially for the physical analysis of chip size packages (CSPs) and the flip-chip. The techniques are not only useful for CSPs and the flip-chip, but also for a variety of single components. Sample preparation time is greatly reduced.

Introduction

VLSI failure analysis techniques requires sophisticated sample preparation techniques so that we can access the heart of a devices without affecting the device’s functionality. This is especially true for the newer VLSI packaging technologies, such as the chip size package (CSP) with a ball grid array (BGA) and the flip-chip package with the BGA or bumps. For the CSP and flip-chip, backside sample preparation techniques [1], [2], [3], [4], [5] have been developed to localize failure sites from backside using contact-less methods, such as emission microscope, laser voltage probing (LVP) [6], [7] and picosecond imaging circuit analysis (PICA) [8]. After localization of failure sites, physical analysis is necessary to identify the root cause of failures.

For CSPs and flip-chip, there are still reliability problems because of solder joint fatigue. Additionally, preparing sample without changing the joint structure is difficult. Sample encapsulation by epoxy and successive dicing and lapping of the sample cross-section are common preparation procedures for the analysis of solder joint interfaces. However, these procedures extend sample preparation time to more than 10 h, and samples are sometimes damaged during the dicing and lapping processes. There is therefore a need for quick and simplified sample preparation techniques.

This paper describes a specially designed sample preparation machine and presents a variety of application results. It also briefly covers our backside thinning techniques.

Section snippets

Development of a sample preparation machine

The main requirements for sample preparation for CSPs and flip-chips are a low-damage process, positioning accuracy and thickness controllability. To meet these requirements, we developed an application-specific machine (Fig. 1) for sample cutting and griding. As a first step to reducing process-induced damage, we immerse the sample in a water bath (Fig. 2), instead of supplying water through a conventional water-jet nozzle. This suppress blade vibration and thereby reduces chipping. Processing

Examples of application results

Typical application results for the sample preparation machine are presented in this section. Since sample thickness tends to increasing with the advancement of packaging technology for higher packaging density, it is becoming important to be able to make samples thinner before starting the physical analysis.

Backside thinning techniques

Fig. 19 shows a dual in-line package (DIP) just after backside thinning was performed by using a diamond drill. Epoxy is used to fix the chip. Fig. 20 shows a quad flat package (QFP) after backside thinning and successive mirror polishing were performed. Emission from MOSFETs can be clearly detected with an IR microscope. The lower side of the chip appears dark because the part was not mirror polished enough.

Summary

A low-damage sample preparation machine achieves simple and effective sample preparation for the physical analysis of the CSP and the flip-chip. The machine also works well for a variety of single components. As a result, sample preparation time is greatly reduced for many kinds of samples.

Acknowledgements

The authors thank K. Moriya for his continuous encouragement. They also thank Y. shionoya, K. Mafune and J. Kinoshita for their support in the failure analysis work.

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