Introductory Invited Paper
A review of electrostatic discharge (ESD) in advanced semiconductor technology

https://doi.org/10.1016/j.microrel.2003.10.004Get rights and content

Abstract

Electrostatic discharge protection in semiconductors have undergone both revolutionary and evolutionary changes to maintain pace with the rapidly scaling and changing environment of advanced semiconductor technologies. As a result, it is an area of continuous discovery in both semiconductor development, and design. ESD phenomenon remains a research and development arena for new innovation, invention, and initiatives. In this paper, an introduction to electrostatic discharge protection in semiconductors will be reviewed.

Introduction

The electrostatic discharge (ESD) phenomenon interested mankind since its first discovery by Thales of Miletus in approximately 600 B.C.E with the discovery of the electrostatic attraction between amber and hay. Thales of Miletus, one of the Seven Sages of Greece, first noted that amber attracted strands of hay. As a result, the word “elecktron” comes from the Greek word for amber. Electrostatics intrigued many scientists through history––Coulomb, Faraday, Franklin, Gauss, Maxwell, and others. In time, there became less interest in electrostatics and a greater interest in electromagnetism, electrodynamics and the new engineering specialties, materials, and inventions that developed.

Electrostatic discharge and electrical breakdown in materials continued to be of interest to physicists, engineers and material scientists to understand the electrical breakdown phenomenon. Electrical breakdown of gases, liquids and solids remained an important area of interest because of the importance in understanding conduction and breakdown in materials, and the design of new materials. Many scientists have focused on the understanding of conduction in new materials and the electrical breakdown. Paschen, in 1889, discussed electrical breakdown in gases and noted the universal nature of breakdown voltage, gas pressure and the spacing of the electrodes. Townsend, in 1915, discussed the concept that avalanche phenomenon occurs at a critical avalanche height which relates the probability coefficient of ionization and the electrical gap, which is now known as the Townsend criteria [1]. These early researchers wanted to understand the relationship between the electrical fields and the molecular atoms. As noted by Arthur Von Hippel, “the internal electric fields create the molecular organization of matter, the external fields tend to unbalance it in actions ranging from reversible polarization and carrier motion to irreversible transformation and destruction” [2].

Electrostatic discharge events occur in our daily experience. As you wake up in the morning to a lightning storm, from walking on the carpet, touching the door knob, plugging your palm reader into its socket, getting in your car, pumping gasoline in your car, and putting the key in the ignition, it is possible to experience ESD events before you even get to work in the morning; the materials, the air humidity, the electronic equipment, and the procedures all influence how these ESD events manifest themselves. It is because it is part of our daily experience that it was one of the earliest scientific discoveries by mankind, and at the same time does not seem to ever go away.

Today, there are two major focuses in electrostatic discharge engineering. One key focus area remains in the area of material research for development of materials with desired conductivity characteristics. Material scientists are interested in dissipating electrostatic charge in a fashion that is non-destructive to electronics, tooling, and humans. Materials are being synthesized from conductive polymers to conductive resins (e.g. addition of carbon) to achieve the desired conductivity in plastic trays, crates, shoes, floor tiles to floor waxes.

The second area of focus is electronic equipment. The electronic equipment sector where electrostatic discharge and electrical over-stress are issues includes electronic components, cards, and systems. ESD and EOS are a concern at all stages of production of a system. What does change is the nature of the ESD event and its ramifications to the system or component. In semiconductors, even prior to completion of the semiconductor component, ESD is a concern in different tooling sectors. The type of discharge and its impact shifts as the product moves from the wafer level to the final system construction. On a semiconductor wafer, etching, testing, and dicing can introduce ESD concerns if proper procedures and design rules are in place to avoid concerns. A key solution to avoid ESD concerns is to build reliability into the semiconductor components. This is best achieved by establishing a disciplined system of ESD structures, circuits, practices, design rules, testing and computer aided design (CAD) design checking and verification. Even with the establishment of the “ideal” ESD system, with the ever-changing environment of semiconductor technologies and semiconductor scaling, new issues and problems reoccur. When we believe we are getting closer to the cure for ESD protection of semiconductors, the cure is only temporal, because today’s solutions may not be applicable for tomorrow’s technology applications. New discovery, invention, and innovation continues to occur in the ESD protection field with component scaling, and the introduction of new technologies, and new product applications.

ESD protection concerns cycle with technology revolution and evolution for the last 30 years and have continued as we have entered a new millennium. Semiconductor technology revolutions have been introduction of new materials, features, devices, technology types, and integration. Semiconductor technology evolutions results from technology scaling of geometric dimensions and lower power supplies. This constant cycle has occurred in ESD development from the transitions from NMOS to CMOS, CMOS to SOI, BiCMOS to RF BiCMOS silicon germanium, and magneto-resistor (MR) to tunneling magneto-resistor (TMR). Within each of these technology disciplines, evolutionary changes also lead to ESD setbacks or advancements depending on whether the dimensional scaling impacts ESD scaling. Evolutionary changes in CMOS included LOCOS to shallow trench isolation (STI), diffused n-well to retrograde implanted wells, non-salicide to salicide junctions, titanium (Ti) to cobalt (Co), tapered via to tungsten (W) stud, aluminum (Al) to copper (Cu), silicon dioxide to low-k materials and p+ to p substrate; all of these influenced ESD robustness of semiconductor products with both positive and negative ramifications. In this paper, we will review the technological transitions and how they influenced ESD. We will also discuss innovations, inventions and technological advancements that lead to improved ESD protection.

Section snippets

Early semiconductor technologies

Prior to the development of CMOS technology, bipolar and NMOS technologies dominated the semiconductor industry until the mid-1980s. Early ESD research focused on the development of physical models to understand the power-to-failure in diodes, bipolar transistors, and NMOS technology. Early researchers (e.g., Wunsch and Bell [3], Tasca [4], Brown [5], Alexander [6], and Enlow [7], Pierce and Mason [8], Whalen and Domingos [9], [10]) developed early physical models to explain the relationship

CMOS technology

With the revolution from NMOS to CMOS technology, Shockley diodes or silicon controlled rectifiers (SCR) were introduced by Avery [13]. In an NMOS technology, a p-type region was not available for usage as a diode or as a lateral pnp. With the introduction of CMOS technology, lateral pnp and lateral npn parasitic transistors were available allowing formation of a pnpn lateral structure. The typical lateral pnpn formed in CMOS consists of a p+ diffusion, an n-well, a p substrate and an n+

LOCOS to shallow trench isolation (STI)

With the revolutionary transition from LOCOS to STI, parasitics and ESD device operation was significantly influenced. Device engineers were focused on the influence of the MOSFET performance but little thought was given to ESD protection in a mainstream CMOS STI-defined technology.

With the introduction of STI, parasitic lateral npn, pnp, and pnpn devices were significantly altered [16]. ESD STI-bound diode operation had significant differences in the design and operation as a result of the low

Silicon on insulator

Early ESD protection work was initiated in silicon-on-insulator (SOI) technology demonstrating that ESD protection in SOI may be a challenge and impediment of SOI to become a mainstream technology for the semiconductor industry. Good SOI ESD protection was demonstrated by niche market vendors who required ESD robustness and reliability for space and military applications. In SOI technology, a buried oxide (BOX) film separates the semiconductor devices from the bulk substrate. From an ESD

Silicon to silicon germanium

At that time there was an accelerated interest in the robustness of semiconductor to withstand electromagnetic pulse (EMP) events, bipolar transistors and diodes were critical components of memory and logic technology. As a result, ESD researchists focused significantly on silicon bipolar junction transistor (BJT) devices and diodes. Early workers were interested in the ESD robustness as a function of pulse width for understanding broad-band EMP effects. The two interests were primarily in

Magneto-resistor (MR) read recording heads

In the disk drive industry, both revolutionary and evolutionary changes are ongoing for recording head scaling to provide density and low cost. The scaling trend in this industry is leading to continued increase in the ESD sensitivity of the recording elements. ESD concerns in the disk drive industry was evident in 1993 in thin film magneto-resistor (MR) recording heads. In the magnetic recording industry, MR heads are constructed on non-silicon substrate wafers; as a result, the standard

ESD technology benchmarking

Advancements in ESD characterization has been limited by the lack of common language, common structures and common testing techniques and analysis. Standardization of common test structures and ESD technology benchmarking will assist the dialogue between customers and foundries. At SEMATECH, in 1994, the first seeds were established to establish common ESD test structures for the semiconductor industry to achieve this goal by an ESD team from major US semiconductor suppliers [45], [46], [47],

ESD checking and verification system

Computer aided design (CAD) of semiconductors has significantly advanced in areas of design layout, device models, timing, checking and verification in all areas. The integration of the CAD tools in a network and methodology which works synergistically has seen significant growth. For ESD design, this has not been true. Where tools have been developed, few tools were integrated with the complete design methodology, leading to the lack of adaptation and support of these tools. In a few cases,

Acknowledgements

I would like to thank Dr. Nino Stojadnovic for the opportunity for the invited paper in the Journal of Microelectronics Reliability. I also would like to thank my summer IBM cooperative interns (Morriseau, Juliano, Ronan, and Watson), IBM co-workers, and ESD engineers for the collaboration, interaction and endeavors in exploring new phenomenon in the ESD discipline.

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