Parametric study on flip chip package with lead-free solder joints by using the probabilistic designing approach
Introduction
Solder fatigue and interface delamination are two major failure modes in flip chip on board (FCOB), caused mainly by mismatch in thermal expansion coefficients between the silicon die and the substrate. Fatigue failures occur as a result of the damage in the solders produced by the cyclic inelastic strains. On the other hand, the peel stress and shear stress between the interface of the die and underfill is the driving force for the interfacial delamination. Previous study on a FCOB with Pb–Sn eutectic solder bumps has shown that the creep strain plays a predominant role on the fatigue life of the FCOB [1]. In [2], effective inelastic strain was used as an indicator for the flip chip solder fatigue prediction. The hydrostatic stress in the solder caused by the constraint effect of the underfill has significant effect on the solder fatigue life as well [1]. There are many factors that influence the stress/strain state in the package, among which the geometric parameters are crucial for reliability and for consideration of optimal design of a package.
Nowadays, the research and development of lead-free solder technology attract more and more attention because of both competitive market pressure and environmental concern. Comparing with numerous researches already done on the reliability issues of flip chip with high lead solders, much less is known about the parametric influence on reliability of a lead-free flip chip package. Under this circumstance, a simulation based probabilistic design approach by using the response surface analysis and Monte Carlo random simulation method is useful tool for investigation of the reliability issues and optimization of a lead-free FCOB.
Section snippets
Geometry model
In order to investigate the effect of packaging parameters on the stress/strain output status of the lead-free soldered flip chip package, which is subjected to a certain kind of the thermal loading history, a 3-D parametric finite element model for a 5 × 5 mm2 test chip with 96.5Sn–3.5Ag solder bumps is constructed. The chip contains 48 bumps, which are distributed in two rows around the periphery of the die in a staggered configuration.
A 3-D parametric FE model of the FCOB is set up in a
Response surfaces for lead-free FCOB parameters
Previous researches have shown that the geometrical parameters play very important role to the reliability of the 63Sn–37Pb soldered FCOB [9], [10]. However, much less is known about the lead-free solders impact on the corresponding stress/strain output during the packaging process. Therefore, a study on the response surface between the major packaging parameters and the stress/strain state is carried out below.
In order to construct the approximate function between the packaging parameters and
Probabilistic analysis
The random Monte Carlo simulation method based on response surface approximate function is introduced to carry out the probabilistic analysis of the lead-free FCOB in this paper. A sample space containing ten thousand designing points is made by using the latin hypercube sampling (LHS) method, which has a sample memory function so that to reduce the random simulation loops. The input variables of Hj,Pj and Ts are assumed to obey the uniform distribution form and characterized by their lower and
Conclusions
In this paper, a probabilistic design approach based on response surface and Monte Carlo simulation has been successfully used to investigate the inherent function and sensitivity relationship between the major packaging parameters and the related stress/strain value of a 96.5Sn–3.5Ag soldered FCOB.
The results of our studies have shown that the different packaging parameters will influence the output stress/strain state of the package in a very different way and degree. It is indicated that the
Acknowledgements
The research work in this paper is financially supported by the National Natural Science Foundation of China (NSFC) (grant no. 60166001 and 50243018).
References (10)
- et al.
Vertical die crack stresses of flip chip induced in major package assembly processes
Microelectron. Reliab
(2000) Investigation on flip chip solder fatigue with cure-dependent underfil properties
IEEE Trans. Compon. Packag. Technol
(2003)- Qian Z et al. Fatigue life prediction of flip-chips in terms of nonlinear behaviors of solder and underfill. In: Proc...
- et al.
Modelling and analysis of 96.5Sn–3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia circuit board
IEEE Trans. Electron. Packag. Manufact
(2002) - ANSYS User's Manual, Release 5.7,...
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