A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections
Introduction
Integration of Cu with low k dielectrics provided solutions to reduce both RC delay and parasitic capacitance of BEOL interconnections [1], [2], [3]. Fabrication of Cu interconnects with low k or ultra low k dielectrics (deposited by either CVD or spin-on) is challenging in terms of unit module developments [4], [5]. The main challenges are categorized into (a) mechanical integrity such as intrinsic materials strength, adhesion strength of low k films to other layers, and CMP compatibility and (b) chemical behavior such as susceptibility to resist poisoning and compatibilities with etching, stripping and wet clean chemicals [4], [6]. Conventional processes such as etching, ashing and wet clean might no longer be applicable at submicron technology node due to the impact of changes in BEOL deposition technologies [7], [8], [9]. Furthermore, functionality of end product is being tested at wafer and packaging levels for reliability. Therefore, a robust process integration of Cu with low k dielectrics must involve the appropriate definition of integration scheme, specific unit module developments and reliability study.
Cleaning of wafers must be performed at certain critical processing steps such as etch/photoresist stripping, oxidation, deposition, and post-CMP residue removal [10], [11]. Wet clean processes after via etch, metal 2 trench etch and Cu cap etch were normally implemented for the dual damascene integration. Post via etch clean and trench etch clean were designed to remove polymeric residues from sidewalls of via and trench respectively. Cu cap etch process was to open vias to the underlying Cu metallization. Etch chemistry left the Cu surface contaminated with CFx, CuFx, CuO and Cu2O [12]. Removal of these contaminations from damascene structure is essential prior to barrier deposition at BEOL interconnection. This cleaning must effectively remove polymeric residues resulting from etch and re-sputtered Cu on via and trench sidewalls [6], [13], [14]. The latter is to ensure that no Cu is entrapped between dielectrics and barrier which otherwise may lead to leakage between metal lines and poor reliability. Cu diffusion in dielectrics at interconnect levels leads to shorts and leakage paths between conductors. Apart from removing residues and contaminants, wet clean chemistry must not lead to increase in critical dimension (CD) and final via and trench sidewall profile [15]. Along these lines, Louis et al. [16] studied and reported probable mechanisms and cleaning efficiency of different Cu compatible chemistries after plasma etch treatment of Cu interconnection with low k dielectric.
Both fluoride- and amine-based wet clean mixtures are commonly employed for wafer cleaning treatments [17]. Singh et al. [18] compared the attractive features of single wafer processing with batch processing in terms of cycle time reduction, better control of surface and interface properties and defect densities reduction. Single wafer processing for BEOL applications has been reported and applied to post-etch/ash residue removal [19], [20]. In this study, we have performed a three-way split of post-etch clean treatments in the fabrication of dual damascene interconnects. We evaluated the wet clean of wafers using conventional batch spray and the more recent single wafer wet clean processing systems. Electrical and reliability performance of via contacts and interspersed metal comb structures were investigated and discussed here.
Section snippets
Experimental procedures
We fabricated double level Cu interconnects with CVD low k film SiOCH (k ∼ 2.9) for 130 nm technology node on 200 mm wafers using dual damascene architecture with “via-first-trench-next” approach. Undoped silicate glass (USG) was used as top hardmask while SiC was used as bottom hardmask, middle etch stop layer and Cu cap layer in the integration scheme. The passivation consisted of composite layers of SiNx/USG. Fig. 1 depicts a schematic cross-section of the dual damascene metallization. The low
Electrical performance of dense via chains
CD variation of via bottom for the three wet clean schemes was within ±10% of 200 nm. Resistance change of dense via chains could therefore, be related to the difference in wet clean processing. Fig. 2(a) and (b) show the representative SEM micrographs of isolated vias after SiC cap etch and post-etch clean with scheme 1 respectively. Polymeric residues adhering to trench sidewall and bottom of via before wet clean treatment were identified in Fig. 2(a). After wet clean with Chemical A in
Conclusions
Based on the above observation, we demonstrated integration of double level Cu/CVD low k SiOCH interconnects for 130 nm technology node on 200 mm wafers. Excellent electrical yields (>95% at dense via chains and interspersed metal comb structures) and reliability performance were achieved with optimized wet clean scheme 1. It is concluded that good control of the contact resistance was maintained through optimized processing conditions with the single wafer wet clean system using fluoride-based
Acknowledgements
The authors would like to thank team members of Semiconductor Process Technologies Lab of the Institute of Microelectronics for the wafer fabrication and electrical testing.
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