Elsevier

Microelectronics Reliability

Volume 45, Issues 3–4, March–April 2005, Pages 517-525
Microelectronics Reliability

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

https://doi.org/10.1016/j.microrel.2004.07.007Get rights and content

Abstract

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.

Introduction

Integration of Cu with low k dielectrics provided solutions to reduce both RC delay and parasitic capacitance of BEOL interconnections [1], [2], [3]. Fabrication of Cu interconnects with low k or ultra low k dielectrics (deposited by either CVD or spin-on) is challenging in terms of unit module developments [4], [5]. The main challenges are categorized into (a) mechanical integrity such as intrinsic materials strength, adhesion strength of low k films to other layers, and CMP compatibility and (b) chemical behavior such as susceptibility to resist poisoning and compatibilities with etching, stripping and wet clean chemicals [4], [6]. Conventional processes such as etching, ashing and wet clean might no longer be applicable at submicron technology node due to the impact of changes in BEOL deposition technologies [7], [8], [9]. Furthermore, functionality of end product is being tested at wafer and packaging levels for reliability. Therefore, a robust process integration of Cu with low k dielectrics must involve the appropriate definition of integration scheme, specific unit module developments and reliability study.

Cleaning of wafers must be performed at certain critical processing steps such as etch/photoresist stripping, oxidation, deposition, and post-CMP residue removal [10], [11]. Wet clean processes after via etch, metal 2 trench etch and Cu cap etch were normally implemented for the dual damascene integration. Post via etch clean and trench etch clean were designed to remove polymeric residues from sidewalls of via and trench respectively. Cu cap etch process was to open vias to the underlying Cu metallization. Etch chemistry left the Cu surface contaminated with CFx, CuFx, CuO and Cu2O [12]. Removal of these contaminations from damascene structure is essential prior to barrier deposition at BEOL interconnection. This cleaning must effectively remove polymeric residues resulting from etch and re-sputtered Cu on via and trench sidewalls [6], [13], [14]. The latter is to ensure that no Cu is entrapped between dielectrics and barrier which otherwise may lead to leakage between metal lines and poor reliability. Cu diffusion in dielectrics at interconnect levels leads to shorts and leakage paths between conductors. Apart from removing residues and contaminants, wet clean chemistry must not lead to increase in critical dimension (CD) and final via and trench sidewall profile [15]. Along these lines, Louis et al. [16] studied and reported probable mechanisms and cleaning efficiency of different Cu compatible chemistries after plasma etch treatment of Cu interconnection with low k dielectric.

Both fluoride- and amine-based wet clean mixtures are commonly employed for wafer cleaning treatments [17]. Singh et al. [18] compared the attractive features of single wafer processing with batch processing in terms of cycle time reduction, better control of surface and interface properties and defect densities reduction. Single wafer processing for BEOL applications has been reported and applied to post-etch/ash residue removal [19], [20]. In this study, we have performed a three-way split of post-etch clean treatments in the fabrication of dual damascene interconnects. We evaluated the wet clean of wafers using conventional batch spray and the more recent single wafer wet clean processing systems. Electrical and reliability performance of via contacts and interspersed metal comb structures were investigated and discussed here.

Section snippets

Experimental procedures

We fabricated double level Cu interconnects with CVD low k film SiOCH (k  2.9) for 130 nm technology node on 200 mm wafers using dual damascene architecture with “via-first-trench-next” approach. Undoped silicate glass (USG) was used as top hardmask while SiC was used as bottom hardmask, middle etch stop layer and Cu cap layer in the integration scheme. The passivation consisted of composite layers of SiNx/USG. Fig. 1 depicts a schematic cross-section of the dual damascene metallization. The low

Electrical performance of dense via chains

CD variation of via bottom for the three wet clean schemes was within ±10% of 200 nm. Resistance change of dense via chains could therefore, be related to the difference in wet clean processing. Fig. 2(a) and (b) show the representative SEM micrographs of isolated vias after SiC cap etch and post-etch clean with scheme 1 respectively. Polymeric residues adhering to trench sidewall and bottom of via before wet clean treatment were identified in Fig. 2(a). After wet clean with Chemical A in

Conclusions

Based on the above observation, we demonstrated integration of double level Cu/CVD low k SiOCH interconnects for 130 nm technology node on 200 mm wafers. Excellent electrical yields (>95% at dense via chains and interspersed metal comb structures) and reliability performance were achieved with optimized wet clean scheme 1. It is concluded that good control of the contact resistance was maintained through optimized processing conditions with the single wafer wet clean system using fluoride-based

Acknowledgements

The authors would like to thank team members of Semiconductor Process Technologies Lab of the Institute of Microelectronics for the wafer fabrication and electrical testing.

References (28)

  • Kim TS, McKerrow AJ, Hong ZZ, Kirkpatrick B, Park H, Hong H, et al. Integration of organosilicate glasses (OSG) in high...
  • T. Hattori et al.

    Contamination removal by single-wafer spin cleaning with repetitive use of ozonized water and dilute HF

    J. Electrochem. Soc.

    (1998)
  • M. Heyns et al.

    Advanced wet and dry cleaning coming together for next generation

    Solid State Technol.

    (1999)
  • Gambino J, Stamper A, McDevitt T, McGahay V, Luce S, Pricer T, et al. Integration of copper with low-k dielectrics for...
  • Cited by (13)

    • Recent advances and future developments in PVA brush scrubbing cleaning: A review

      2022, Materials Science in Semiconductor Processing
      Citation Excerpt :

      Researchers have studied that optimized brush scrubbing could be effective if applied properly by adjusting the rotational brush speed and pressure. Tsang et al. [54] found that the optimized cleaning process of wet cleaning could improve the electrical and reliability performance of Cu/low k interconnections. Scholars then adopted their idea overwide to optimize PVA brush scrubbing similarly.

    • Metal Surface Chemical Composition and Morphology

      2018, Handbook of Silicon Wafer Cleaning Technology
    • Effect of composition of post etch residues (PER) on their removal in choline chloride-malonic acid deep eutectic solvent (DES) system

      2014, Microelectronic Engineering
      Citation Excerpt :

      The nature of PER is highly variable and depends on plasma chemistry and conditions as well as interaction of plasma with materials that are integrated [5]. Semi-aqueous fluoride formulations containing organic solvent(s), water, fluoride source and inhibitor(s) are currently popular for the removal of many types of post etch residues [6–8]. Dilute HF solutions with very low oxygen content also appear to be effective for PER removal [9].

    • Post-etch residue removal using choline chloride-malonic acid deep eutectic solvent (DES)

      2013, Microelectronic Engineering
      Citation Excerpt :

      The efficiency of residue removal is affected not only by the material complexity but also by where the residue is formed. Currently, semi-aqueous fluoride (SAF) cleaning formulations that contain aprotic solvents, amines, fluorides, water and in some cases, corrosion inhibitors are cleaning agents of choice in the semiconductor industry [5–8]. However, the downside of these formulations is the use of solvents that are not very environmentally friendly [9].

    View all citing articles on Scopus
    View full text