Reliability study of Power RF LDMOS for Radar Application

In this paper, a novel silicon on insulator (SOI) lateral diffused metal oxide semiconductor (LDMOS) transistor with high voltage and high frequency performance is presented. In this work we try to reduce the electric field crowding in the drift region. The proposed structure consists of a metal in the buried oxide and also connected to the source. The inserted metal attracts the electric field lines in the buried oxide. It causes 67% improvement in the breakdown voltage in comparison with a conventional SOI-LDMOS (C-LDMOS). Our simulations with two dimensional ATLAS simulator show that the gate-drain capacitance improves in the proposed structure. The unilateral power gain also enhances. So, the proposed structure is suitable for high voltage and high frequency applications.

This paper presents a compact model for the lateral double-diffused MOS transistor in which ion implantation is employed in the channel region. We show that the conventional LDMOS device models which do not include specifics of the implanted channel region cannot accurately predict behavior of such structure. We then propose a new physics based model which employs surface potential in the device. The model gives a robust formulation for both the channel and the drift regions and can accurately describe the performance of the ion implanted channel LDMOS structure.

An innovative reliability test bench dedicated to RF power devices is currently implemented. This bench allows to apply both electric and thermal stress for lifetime test under radar pulsed RF conditions. This paper presents the first investigation findings of critical electrical parameter degradations after thermal and electrical ageing. It shows that the tracking of a set of parameters (drain–source current, on-state resistance, threshold voltage, feedback capacitance and transconductance) can give insight into the hot carrier injection phenomenon for a RF n⁻ channel lateral DMOS (N⁻ LDMOS) working under pulsed conditions.

We present in this paper results of comparative reliability study of three accelerated ageing tests applied on power RF LDMOS: Thermal Shock Tests (TST, air-air test), Thermal Cycling Tests (TCT, air-air test) and High Temperature Storage Life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The results obtained show the variation and the Device’s performance quantitative shifts for some macroscopic electric parameters such as threshold voltage (V_th), transconductance (G_m), drain-source current (I_ds), on-state resistance (R_{ds_on}) and feedback capacitance (C_rs) under various ageing tests. To understand the degradation phenomena that appear after ageing, we used a new electro-thermal model implemented in Agilent’s ADS as a reliability tool.