Low voltage SILC and P- and N-MOSFET gate oxide reliability☆
Introduction
The predicted reliability limit of MOS gate oxide has been shifted towards thinner and thinner oxides as more data has been collected. So 2.5–1 nm thick silicon oxides continue to be a critical component as gate insulators in MOSFETs. Recent articles have indicated that intrinsic gate-oxide reliability has probably not been a real issue for the thicker oxides (tox ⩾ 3 nm) at the operating voltages employed, but the gate oxide life time is definitively a crucial issue for thinner oxides (tox ⩽ 2 nm) [1]. The oxide reliability is characterized by the charge or the time to breakdown at the operating voltage. These quantities are reached by extrapolation from oxide lifetime data obtained under accelerated stress conditions (high voltage and/or high temperatures). However it is not certain that high voltage data could be extrapolated to low voltage data (1.5–1 V). In order to improve the extrapolation accuracy, work has been done on the voltage dependence of the defect generation rate leading to breakdown. DiMaria has shown that, independently of the assumed physical mechanism of defect creation, the charge to breakdown is inversely related to the defect creation initial rate which can be measured at low injected charge where the defect density increases linearly with the injected charge [2]. For thin oxides (3–5 nm) the rate does not depend on defect type. It can be measured, by monitoring the increase of oxide bulk neutral traps. In these oxides, the gate current at low voltage (in inversion or accumulation regime) is due, in N-MOSFET to electrons tunneling from the cathode to the anode via neutral bulk oxide traps and in P-MOSFET to electrons or holes. Therefore the as-fabricated gate current, J0, depends on the defect density N, and its increase after stress ΔJ on ΔN. At low injected charge, Δ J/J0 varies linearly with the injected charge and is equal to ΔN/N0. Therefore the SILC can be used to obtain the defect generation rate.
In 2.5–1 nm thick oxide, J0 in inversion or accumulation regime, is mainly a direct tunneling current, which depends no more on N and which increases drastically as the oxide thickness decreases. Consequently, at ΔN constant, ΔJ/J0 decreases with the oxide thickness and is no longer equal to ΔN/N. Therefore, as it is seen in Fig. 1, the SILC ceases to be a sensitive tool to monitor the oxide degradation, but, with these ultra-thin oxides, in the gate voltage range corresponding to the depletion regime, a gate current becomes measurable before stress, and a large gate current increase is observed after stress. At room temperature (Fig. 2) in N-MOSFET the current is mainly due to electron tunneling, against the oxide field, from one electrode to the other via either interface states or bulk oxide traps, and in P-MOSFET to holes or electrons [3], [4], [5]. Therefore J0 depends on N and ΔJ on ΔN, where J0 is the gate current before stress in depletion regime, N is the defect density via which the carriers tunnel. The current increase ΔJ is referred to as LVSILC (low voltage SILC). The question is: can the LVSIC be used to monitor the oxide reliability at operating voltages? Previous studies on N-MOSFETs, with oxide thicknesses ranging from 1.2 nm to 2.5 nm, have shown that, on the one hand, stress created interface states, measured by the charge pumping method, induce a drain current degradation but not the oxide breakdown, and that, on the other hand, a large LVSILC increase is always observed before the oxide breakdown [4], [6], [7], [8]. Therefore the LVSILC can possibly be used to monitor the oxide reliability. The results presented in this article confirm that the LVSILC is a sensitive tool to study the oxide reliability. More work has been done on N- than on P-MOSFETs, and the aim of this work was to study the degradation at low voltage in P-MOSFETs, by monitoring the LVSILC, and to compare the results with those obtained with N-MOSFETs. Usually P-MOSFETs and N-MOSFETs are stressed respectively at negative and positive voltages because they are their respective operating voltage polarizations. In this work, in both cases, negative and positive stresses have been realized in order to gather more information on the degradation mechanism.
Section snippets
Devices and experiments
p+ Poly-Si gate P-MOSFETs (or capacitors) and n+ poly-Si gate N-MOSFETs (or capacitors), with pocket implants, used in this work were fabricated by the CEA-LETI (French laboratory “d’Electronique, de Technologie et d’Instrumentation”) using a standard process compatible with most advanced CMOS technologies. The gate oxide thickness measured by ellipsometry and CV measurements is approximately 2.1 nm. Substrate and polycrystalline silicon gate dopings are respectively close to 1.7 × 1018 and 5 × 1019
Conclusion
It has been shown that, however the LVSILC defect origin may be, it is a sensitive tool to monitor the oxide degradations induced by constant low voltage stresses and a relation seems to exist between LVSILC and oxide breakdown. For the same injected charge, negative stresses are more degrading at low voltages than positive ones for P- and N-MOSFETs, and they degrade similarly N- or P-MOSFETs. At their respective operating voltages, the gate current variation is negligible until the oxide
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2023, Journal of Applied Physics
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An earlier version of this paper was published in Proceedings of 24th International Conference on Microelectronics (MIEL 2004), 16–19 May, Nis, Serbia and Montenegro 2004, Vol. 2, pp. 641–644.