Effects of electrical stressing in power VDMOSFETs

Abstract

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon ${\mathrm{Si}}_{\mathrm{o}}^{}$ defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps ${\mathrm{Si}}_{\mathrm{o}}^{+}$ to interface-trap precursors Si_s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects ${\mathrm{Si}}_{\mathrm{o}}^{}{\mathrm{Si}}_{\mathrm{o}}$ is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si_s–H with the charged oxide traps ${\mathrm{Si}}_{\mathrm{o}}^{+}{\mathrm{Si}}_{\mathrm{o}}$ and H⁺ ions are proposed to be responsible for interface trap buildup.

Introduction

Power VDMOSFETs are attractive devices for high-frequency switching power supplies in communication satellites, but an important requirement for these applications is their high radiation tolerance. Namely, over the years of communication satellite mission, even in low-Earth orbits these devices can accumulate the total dose up to 10 krad (SiO₂), while in high orbits this dose can be as high as 1 Mrad (SiO₂) [1].

It is well known that the ionising radiation induced gate oxide-trapped charge and interface traps cause the threshold voltage shift, transconductance reduction, leakage current increase, and breakdown voltage reduction in power VDMOSFETs [2], [3], [4]. The negative threshold voltage shift is, undoubtedly, the most serious problem in the commercial devices since it may cause a change of their operation mode from enhancement to depletion, thus leading to a faulty operation of switching power supplies. Even the radiation-hardened devices may fail as a result of reduction in current-drive capability owing to channel carrier mobility degradation and/or positive threshold voltage shift [2].

With increasing utilization of MOS technology for the realization of power devices and ICs, the interest in ultra-thick gate oxides has steadily grown, and investigations of related reliability issues have recently gained in importance [5], [6], [7], [8]. Recent investigations by Picard et al. [5], [6] have revealed the effects of gate bias stressing and ionising radiation on electrical parameters of power VDMOSFETs to be very similar (as earlier observed in CMOS devices [9]), but their analysis of responsible mechanisms has remained in the scope of qualitative description. Actually, their work was aimed at utilizing the gate bias stressing for radiation hardening of VDMOSFETs [5] and developing the device selection method for application in radiation environment [6]. The former idea appeared to be completely inapplicable [10], while the latter one sounds promising; in both cases, detailed analysis of mechanisms responsible for behaviour of device parameters during stressing is required.

In this paper, the results of our detailed analyses of the effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities, are reviewed [10], [11], [12], [13]. The data are analysed in terms of the mechanisms responsible for the oxide-trapped charge and interface trap buildup, and the model which explains in detail the experimental data is proposed.