Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey
Introduction
Despite the promising recent achievements with respect to the integration of Hf-based high-κ materials (including HfO2, (nitrided) Hf-silicates and Hf-aluminates) into poly-Si based CMOS, the VT/Vfb-control (for all known Hf-based materials) and -instability problem (for certain of those materials and stacks) are persisting technological bottlenecks of paramount importance. These impeding issues concerning the threshold and flatband voltage of both NMOS and PMOS devices are obstructing the practical use of first generation high-κ stacks for device fabrication.
The VT-instability, caused by charges in the dielectric, can be dramatically mitigated e.g. by using a HfSiON-based gate stack in conjunction with poly-Si [1] at the expense of the κ-value however, making the latter material a viable candidate for 65 nm LSTP applications, if apt channel engineering and relaxed device specs can be applied.
The issue of the shifted VT by approximately +0.3 V for NMOS up to −0.6 V for PMOS remains a generic predicament for the 45 nm HP, LOP as well as LSTP node using a high-κ/poly gate stack however and constitutes the focus of this paper.
The alleged mechanism behind this VT-shift is generally referred to as Fermi Level Pinning (FLP) [2], [3], caused by chemical interaction between incompletely coordinated Hf-atoms with Si-atoms at the poly-Si/high-κ interface, causing the formation of energy levels in the band gap of Si close to the conduction band and ‘pinning’ the electrode’s Fermi level. In this paper we do not discuss the details of this mechanism but survey the potential solutions we have evaluated in order to remove this ‘brick wall’.
Section snippets
Experimental
The flatband voltage shift ΔVfb can most easily be extracted from simple large-area capacitors (e.g. 100 × 100 and 50 × 50 μm2), either with or without field isolation. In order to establish the occurrence of FLP more clearly, in selected cases HFCV-measurements were done on noth p+ and n+ devices on n-type Si. If no FLP would occur, the curves should be separated by Eg(Si) = 1.1V (see Fig. 1).
Extraction of (Δ)VT and performance figures require both large area and scaled (Lg, min ∼ 70 nm) optimized
Results and discussion
We have extensively investigated several non-trivial options to avoid FLP or ‘unpin’ the Fermi level for a Hf-based high-κ stack with a poly-Si electrode, including (1) bulk modifications of the dielectric stack such as stuffing the HfO2 with Si and/or N or via so-called ‘laminated’ layers, (2) implementation of thin barrier or capping layers (HfSiON, SiO2, SiN, SiC and Al2O3) or (3) changing the electrode material or its deposition chemistry by e.g. using a SiGe electrode, including a pure Ge
Conclusion
Fermi level pinning is a fundamental problem for poly-Si/high-κ integration and is most likely related to Hf-Si interaction. Neither ‘hiding’ the HfO2 (cap layer) nor diluting it (alternative dielectrics/electrodes) adequately resolves the problem. It has not been cured by any of the above listed practical attempts and remains a showstopper for 45 nm CMOS integration. For the 45 nm node, metal-gated transistors and FUSI are enabling technologies that outperform poly/SiON devices in terms of
Acknowledgements
The authors wish to thank the IMEC pilot line for the processing and the AMSIMEC group for electrical measurements.
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