Integrated CMOS GSM baseband channel selecting filters realized using switched capacitor finite impulse response technique

Abstract

A problem of the design and optimization of analog channel selecting filters, which are needed in wireless communication systems, is considered and evaluated in this paper on an example of the baseband GSM (global system for mobile telephony) channel filter. Two versions of this filter, both designed by the authors using switched-capacitor finite impulse response (SC FIR) technique, are presented and compared to each other as well as to other concurrent designs. In order to fully and plausibly compare the both filter versions (the newer and the elder one), the authors decided to design and fabricate both filters using the same technology, i.e., the technology of the elder filter version, which is the two metal, two poly CYE CMOS 0.8 μm process. The conclusions, which have been drawn, are, however, general and to a large extent technology independent.

Although both presented filters are switched-capacitor (SC) finite impulse response (FIR) systems [Dąbrowski A, Cetnarowicz D, Długosz R, Pawłowski P. Design and optimisation of integrated CMOS FIR SC channel filter for a GSM Receiver, European Conference on Circuit Theory and Design, Helsinki, 28–31 August 2001. p I.265; Długosz R, Dąbrowski A, Pawłowski P. Design and measurement results of the GSM SC FIR channel filter realized in CMOS 0.8 μm technology. In: 9th international conference mixed design of integrated circuits and systems, 2002. p. 607–12] they essentially differ to each other as they are based on two quite different SC FIR delay line structures. In the first filter version Gillingham delay elements [Gillingham P. Stray-free switched-capacitor unit delay circuit. Electron lett 1984;20(7):308–10] are used, while in the second version even and odd delay elements [Dąbrowski A. Multirate and multiphase switched-capacitors circuits, London: Chapman & Hall; 1997; Dąbrowski A, Menzi U, Moschytz GS. Design of switched-capacitor FIR filters with application to a low-power MFSK receiver. IEE Proceedings-G 1992;139(4):450] are alternately connected to form the delay line. In this way an interesting comparison of these two SC delay line concepts has been possible.

It should also be stressed that the frequency responses of both presented filters have been designed using the same technique, i.e., the Kaiser window of order N = 31. The upper frequency is in both cases equal to 500 kHz and the frequency of the controlling clock generator is equal to 1 MHz.

The filter with Gillingham delay elements dissipates 30 mW with the 3 V supply voltage and occupies 2.2 mm². On the contrary, the even–odd SC FIR filter dissipates 18 mW only with the 3 V supply voltage and occupies 2.4 mm². Moreover, the newer filter version has the stopband attenuation greater by about 10 dB than the previous version.

Introduction

Some years ago, due to sudden and revolutionary development of various digital techniques as well as due to the rising area of their applications, it seemed probable that analog electronic systems can no longer be competitive and have approached their end. Nowadays it is clear that this opinion has proved to be false. On one hand, the surrounding world is analog at the macroscopic scale and the analog electronic systems will therefore always be used at least on the border between the analog and the digital world. On the other hand, analog solutions occur to be better for many applications (e.g., in the speed, cost, complexity, power consumption, etc.) than their all-digital counterparts. This is exactly the case for the application presented in this paper.

We present results of the design and optimization of the GSM (global system for mobile telephony) baseband channel selecting filter. Generally, two basic approaches are possible to this end [12]. The first one, referred to as the single-stage approach, is based on the direct A/D (analog-to-digital) signal conversion as is shown in Fig. 1. The second approach consists in a two-stage processing with an analog channel filter in the first stage followed by the A/D converter and the digital post-processor in the second stage, cf. Fig. 2.

The analog-to-digital converter needed in the two-stage approach is much simpler (since resolution of only 6–8 bits is required as opposed to 14–16 bits for the single-stage approach). Consequently, using the two-stage approach, power consumption can substantially be reduced (by even 85% [10]) compared with the single-stage approach. Thus, the two-stage approach is clearly advantageous over and above the single-stage approach. Therefore the filters presented in this paper are designed for the two-stage approach.

The presented experimental chip, containing two versions of the designed GSM channel selecting filter, resulted in fact in two particular stages of a long term research project devoted to the design of programmable high performance filters for modern wireless telecommunication systems, i.e., GSM and WCDMA (wideband code division multiple access) [13].

In this paper we consider an interesting and promising class of analog discrete-time (sampled-data) electronic circuits, namely the switched-capacitor finite impulse response (SC FIR) filters [14].

Signal samples are represented in SC filters as charges stored in capacitances (thus also as voltages). These samples are processed using active devices (operational amplifiers) and switches controlled by means of a clock.

One of our goals is to show that the proposed and designed SC FIR filters can successfully be optimized for their application in modern wireless telecommunication systems and that they can have comparable or even better parameters than systems based on other approaches.

Although SC FIR filters have already been considered and presented in the literature, e.g., in [3], [4], [15], their multicriteria optimization especially for the considered application and for the respective CMOS realization, which is just the subject of this paper, has not yet been reported.

One of advantages of our SC FIR filter approach is a relatively low control clock frequency, which must only be twice as high as the maximum signal frequency. Although this is, in principle, also the case for typical infinite impulse response (IIR) filters realized, e.g., with biquadratic sections, the real required clock frequency must for these systems be even 10 times higher than the maximum signal frequency [11]. In consequence, operational amplifiers (OA’s) for our SC FIR filters can be much simpler, cheaper, narrower in the bandwidth, and consuming less chip area and less supply power. This is why we have used quite simple slightly modified Miller OA’s in our chips, cf. Fig. 3.

Another very important advantage of SC filters is that their frequency responses do not depend on values of their capacitances in a general way, but exclusively on particular capacitance ratios. In result, inaccuracies unavoidable in the technological process, which typically influence all capacitors in the entire chip in a similar way, do not practically influence the filter frequency response.

An additional advantage of our filters consists in the fact that the output signal samples are available for a relatively long time equal to a half of the clock period. Such samples can then easily be processed by means of an A/D converter without any additional sample and hold circuits. Certainly, there are also other very important advantages of FIR filters, e.g., absolute stability and the possibility for strictly linear phase response.

The whole family of SC FIR filters contains systems of various structures. There exist basic and composite structures. The latter are compositions of two or more basic structures [1], [2], [5]. Each of them can be characterized by advantages and disadvantages taking such important criteria into account as: chip area, number of active elements, power dissipation, complexity of the clock generator, signal quality, etc. In practice, it is often necessary to seek the compromise for a particular application between all these typically conflicting criteria. This is also the case for our application, in which the chip area and the complexity of the clock generator are the key parameters.

Thus in this paper we have chosen and optimized structures for low chip area and relatively simple clock generator. These are tapped delay-line structures with the so-called even–odd delay elements (cf. Fig. 4) and with Gillingham delay elements (cf. Fig. 5).