Impact of the number of chips on the reliability of the solder balls for wire-bonded stacked-chip ball grid array packages
Introduction
Three-dimensional (3D) packaging technologies have received considerable interest owing to their applications in portable electronic systems. The advantages of the 3D packages include reduced size and weight, greater silicon efficiency, reduced delay and reduced noise. A survey summarized the development of 3D packages before 1998 [1]. Even now, new manufacturing processes and novel types of interconnections of 3D packages are vigorously investigated because of their wide range of applications [2], [3], [4], [5], [6], [7], [8]. Among the various types of 3D packages, one is the stacked chip package, which is used extensively in memory modules, flash dice and system-in-a-chip devices. In spite of the development of some new interconnection technologies, such as insulated sidewall interconnections, ultra-fine interconnections, Copper interconnections at low temperature, wafer bounded technology with dielectric bonding glues, wire bonding remains one of the most widespread interconnect technologies for 3D packages because of its generality of equipments and low cost of manufacturing.
The stacked chip package structure is designed to include more than one chip, so the thermal management of such packages has become very important, and some efforts have been made to yield solutions, by both experimental and simulation analyses [9], [10], [11], [12], [13], [14], [15], [16]. The reliability of stacked chip packages is another subject to be addressed. The causes of the loss in reliability of packages are normally mechanical or thermal. Damage to stacked chip packages includes warpage of packages [17], deflection of wire bonds [18], delamination between interfaces [19] and fatigue of solder joints. Work on the reliability of solder joints indicates that both mechanical behavior and thermal mismatching due to the difference between the coefficients of thermal expansion (CTE) of the packaging materials are detrimental to the fatigue resistance of solder joints. Therefore, experimental vibration and bending tests for the reliability of stacked chip modules have been performed [20], [21], and in some works [22], [23], reliability has been examined using thermal cycling tests (TCT), thermal shock tests, or both mechanical and thermal tests [24], [25]. Computational simulation is an economic way to investigate the reliability of stacked chip packages [26], [27], [28]. However, the number of stacked chips was fixed in the simulation studies referred to above.
The development of wafer-thinning technology has greatly increased the number of stacked chips used in designs of 3D packages [29]. Accordingly, knowledge of the effect of the number of stacked chips on the reliability of such packages is required. This work studies the reliability of solder balls for wire-bonded stacked-chip ball grid array (WB-SC BGA) packages with different number of stacked chips under TCTs by computational simulation. Rather than two-dimensional plane-strain simulation, the three-dimensional finite element method (FEM) was used herein to obtain the stress/strain behavior of packages because the full-field stress/strain results obtained from three-dimensional FEM approached the actual behavior of the packages. The elastic–plastic–creep and viscoplastic properties of solder joints were employed individually in the FEM analyses. The stress/strain history of the solder balls extracted from FEM analysis was employed in three fatigue life prediction models to predict the fatigue life of WB-SC BGA packages.
Section snippets
WB-SC BGA packages
Four WB-SC BGA packages with various numbers of stacked chips—one, two, three and four were the subjects of this study. Fig. 1 depicts an example structure, which is the WB-SC BGA package with four chips. The size of all real chips is 13 mm × 10 mm × 0.2 mm. The mirror chip is mounted between the real chips using non-conductive adhesive as the spacer. The size of the mirror chip is 12.5 mm × 7.5 mm × 0.2 mm. The areas of the BT substrate and the FR-4 printed circuit board (PCB) are 15 mm × 15 mm × 0.55 mm and 25 mm ×
Finite element analysis
Three-dimensional FEM was utilized to obtain the stress–strain behavior of the packages under TCT conditions. The commercial FEM program, ANSYS [30], was used to perform the simulation. The symmetry was such that only one quarter of the package (the shadowed part of Fig. 1) was modeled in the analysis. The center of symmetry of the bottom plane of the PCB was fixed in the simulation. The mesh density for each package was the same in each studied case to ensure that the simulation results were
Fatigue life prediction models
The stress/strain behavior determined by FEM analyses was employed in the models to predict thermal fatigue life. Three fatigue life prediction models—Darveaux’s model, the modified Coffin–Manson model and the fatigue-creep model—were considered in the investigation. Due to the requirement of employed prediction models, the results of the viscoplastic FEM analyses were used in the Darveaux’s model, while the results of elastic–plastic–creep FEM analyses were used in the modified Coffin–Manson
Deformation behavior
Fig. 4 depicts the deformed shapes of the studied WB-SC BGA packages at the end of high-temperature dwelling for the third cycle in the elastic–plastic–creep FEM analyses for solder balls. In the figure, the shadowed area is the deformed shape and the unshadowed area is the area before deformation. The locations of the maximum out-of-plane deformations are the same for all studied packages, at the corner of the upper plane of the molding compound that is farthest from the neutral line (denoted
Conclusions
Three-dimensional FEM analysis was undertaken to simulate the stress/strain behavior of WB-SC BGA packages for various numbers of stacked chips. Two kinds of properties for the solder joints were employed in the FEM analyses individually. The simulated stress/strain results were extracted and considered in three fatigue models to elucidate the effect of the number of stacked chips on reliability of the solder ball under TCT conditions. Based on the results of this study, the following
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