Effect of wafer thinning methods towards fracture strength and topography of silicon die

https://doi.org/10.1016/j.microrel.2005.07.110Get rights and content

Abstract

This paper characterizes die damage resulting from various wafer thinning processes. Die fracture strength is measured using ball breaker test with respect to die surface finish. Further study on surface roughness and topography of each surface finish is obtained by atomic force microscopy (AFM) and scanning electron microscopy (SEM) techniques. Stress relief process with 25 μm removal is able to strengthen 100 μm wafer by 20.4% using chemical wet etch and 75 μm wafer by 36.4% with plasma etch. Relatively, plasma etching shows higher fracture strength and flexibility compared to chemical wet etch. This is due to topography of the finished surface of plasma etch is smoother and rounded, leading to a reduced stress concentration, hence improved fracture strength.

Introduction

Wafer thinning is the key technology in today’s semiconductor technology trend which is heading towards thinner and smaller packages. There are many advantages of using thin chips which include reducing space, allow more functionality per unit volume in a stack die package [1]. Having thinner wafers improves the ability to dissipate heat by lowering the die’s thermal resistance [2]. In some cases, IC packaging demand smaller packaging where silicon is as thin as 30 μm [3]. Therefore to achieve this, the die has to be smaller and thinner as well which makes it become more susceptible to process related failure. To be able to fulfill this requirement, it is essential for the silicon die to possess maximum fracture strength as it improves the ability of the thin wafer to survive the mechanical and thermal stress it is subjected to by handling and further processing. Therefore, understanding the correlation of different thinning methods towards die fracture strength is of utmost importance because it impacts the integrity and reliability of semiconductor packages.

Silicon by nature is hard and brittle material, therefore mechanical grinding is the most common technique utilizing abrasive particles to take out most of the wafer thickness. Most grinding systems use a two-step process where step 1 is coarse grinding and step 2 is fine grinding [4], [5], [6]. The coarse grinding removed most of the thickness, almost 90%. A coarse abrasive grinding wheel (typically 350–500 grit diamond) removes material rapidly, but greatly damages the backside surface of the silicon layer [5], [6]. Fine grinding removes most of the damage [7] and reduce it surface roughness with its abrasive diamond of typically 2000–3000 grit. According to Pei [8], Chen and De Wolf [6] and Hadamovsky [9], back grind silicon wafers causes sub-surface damage to the wafer.

Therefore, there is a need for stress relief processes where it is increasingly important application after mechanical grinding [4]. Each type of stress relief method is aimed at removing the damaged silicon left by conventional grinding steps. Stress induced onto the wafers from mechanical grinding need to be removed by stress relief process and etching is one of the ways to enhance the die strength [4], [10]. There are two types of etching available, which is the wet chemical etch (CE) and dry chemical etch, known as plasma (PE). Wet etching used is an acidic compound containing etchants such as HF and HNO3 [2], [4]. In plasma etching, neutral chemical species such as chlorine or fluorine atoms generated in the plasma diffuse to the substrate, where they react to form volatile products with the layer to be removed [11]. Typical reactor used for plasma etching is downstream etchers (no ions and photons) in which, generally, the plasma is excited using microwaves, detail information could be found in [12]. The neutrals strike the surface at random angles leading to isotropic, rounded features. Typically, feed gas SF6 is used for silicon etching [11], [12]. Plasma etching has highest throughput but highest capital investment as well [13].

From a material point of view, silicon by nature is quite stable, but being brittle makes it prone to breakage. Previous studies shows that the fracture strength of a finished die would be higher if the die surface is finer [14]. Therefore, the present work investigates the effects of stress relief process such as chemical wet etching and plasma treatment on the backside characteristics. Markings left behind by each process in the form of defects and specific backside appearances are examined at two levels: through optical inspection using SEM micrograph and, for greater detail, through atomic force microscopy (AFM). The fracture strength of the die was measured as die breaking load by using ball breaker test.

Section snippets

Experimental

Dummy wafers (pure silicon with no circuits) of 6 in. and (1 1 1) orientation were used in this study. The intrinsic properties of the wafers are assumed to be the same but different in wafer back processing. In the coarse grinding process, abrasive wheels with grit size 320 were used, while the wheels with 2000 grit size were employed in fine-grinding process. After mechanical grinding, some wafers were further surface treated by chemical wet etching or plasma etching at different removal rate,

Effect of wafer back processing towards surface roughness (Ra)

Wafer surface conditions play an important role in die fracture strength. Fig. 2 shows the average surface roughness (Ra) results for wafer B to wafer H. Fig. 2 shows there is a rise in surface roughness after mechanical grinding of 3 μm for both chemical and plasma etched samples. However, 25 μm removal reveals a characteristic reduction in roughness (D, H). Clearly, this shows that 3 μm removal by chemical or plasma etching is insufficient and further removal is able to smoothen or reduce the

Conclusion

The effect of different thinning process dictates the damage level of the back surface condition, which in return dominates the die fracture strength. In this study, it can be concluded that the fracture strength of the processed silicon die is dictated by two important factors, which are surface roughness and the amount of removal thickness by stress relief process. Fracture strength is higher for thicker samples and by comparing samples of the same thickness, larger breaking load is needed

Acknowledgements

The authors would like to express their appreciation to Mark Thomas and K.C. Ling from Wafer Fabrication On Semiconductor, for providing the 100 μm and 75 μm wafers by chemical etch. Dr. Misni and Dr. Javad from Colloidal Lab, University Malaya for assisting the use of atomic force microscopy and Rafidah as well as Ruzita from Failure Analysis On Semiconductor.

References (24)

  • M. Reiche et al.

    Wafer thinning: technique for ultra-thin wafers

    Adv Packag

    (2003)
  • Pei ZJ. Available from:...
  • Cited by (44)

    • Morphological characterization of 325 mesh-grinding-induced defects on silicon wafer surface

      2022, Microelectronics Reliability
      Citation Excerpt :

      Many studies of silicon damage evaluation in relation to grinding are widely reported [5–9]. The defects including deep scratch marks can result in mechanical fracture of silicon wafers and diced chips [10–15]. Therefore, most semiconductor back-surfaces are generally finished by additional fine grinding or other back-lapping processes after the rough grinding process [16].

    • A study on the etching characteristics of atmospheric pressure plasma for single-crystal silicon wafer

      2021, Vacuum
      Citation Excerpt :

      In addition, the thermal resistance (R) depends on the insulation thickness (e) and the thermal conductivity (λ) of the material: R = e/λ [2]. For certain material, the thermal resistance is proportional to the thickness, therefore the reduction of thickness contributes to a higher heat flow and lower thermal resistance [2–4]. The decrease of the thermal resistance can lead to an effective and better system performance.

    • Investigation of material removal characteristics of Si (100) wafer during linear field atmospheric-pressure plasma etching

      2020, Nanotechnology and Precision Engineering
      Citation Excerpt :

      To fulfill the requirement of thinner and smaller semiconductor packages and electronic applications, wafer thinning is a crucial technique. The reduction of wafer thickness includes many advantages: save space, lower the thermal resistance, and allow more functionality per unit volume in a stack die package.1,2 Si wafer is still a key substrate material in a wide range of applications because of its well-known mechanical and electrical properties.

    • Assembly technology development and failure analysis for three-dimensional integrated circuit integration with ultra-thin chip stacking

      2016, Microelectronic Engineering
      Citation Excerpt :

      Conventional wafer back-thinning techniques are considered high-risk in inducing mechanical damage and fractures during fabrication handling and dicing steps, as well as in the subsequent assembly of chip stacking. Given chip damage in different thinning processes, ball breaker test and three-point bending can be used to measure wafer breaking strength [4–5]. The solution of using narrow cavities underneath chip areas generated via microelectromechanical systems has been provided to overcome this issue [6–7].

    View all citing articles on Scopus
    1

    Tel.: +606 6711055; fax: +606 6782262.

    View full text