Elsevier

Microelectronics Reliability

Volume 46, Issues 2–4, February–April 2006, Pages 244-262
Microelectronics Reliability

Introductory Invited Paper
Lead-free 0201 manufacturing, assembly and reliability test results

https://doi.org/10.1016/j.microrel.2005.09.007Get rights and content

Abstract

The trend towards smaller, faster and cheaper electronic devices has led to an increase in the use of 0201 (L  0.02 in.; W  0.01 in.) and even smaller sized passive components. The size advantages of the 0201 component make it a popular choice among design engineers but not among manufacturing engineers. From a manufacturing perspective, the size of the 0201 package poses significant challenges to the printed circuit board (PCB) assembly process. The many challenges with 0201 assembly can be attributed to the solder paste volume, pad design, aperture design, board finish, type of solder paste, pick-and-place and reflow profile. If these factors are not optimized, they will introduce undesirable manufacturing defects. The small size of 0201 packages and undetected manufacturing defects will also raise concerns about their second level interconnect reliability, especially for lead-free solder alloys and surface finishes, with new processes and higher reflow requirements. To determine the optimum conditions, a design-of-experiment (DOE) study was carried out to investigate the effects of these parameters on assembly defects and solder joint reliability.

This paper presents the test results and comparative literature data on the influence of a few key manufacturing parameters and defects associated with the 0201 component using lead-free and tin–lead solder alloys. Data pertaining to component shear strength before and after isothermal aging at 150 °C and intermetallic growth up to 500 h of aging are presented. A number of test vehicles were also subjected to thermal cycling (1500 cycles) in the range of −55/100 °C to determine the solder fatigue behavior. Shear test results for test vehicles subjected to thermal cycling is also presented. In addition, optical microscopy analysis of solder joint behavior during thermal cycling showing the progress of the solder damage and cross-sectional photos taken at 1500 cycles is included.

Introduction

Passives are used throughout electronic systems to provide the functions of resistance, capacitance and inductance. More than 10 discrete passives are generally used for every active component in a typical electronic system. Passives account for 90% of all components, 40% of board area and 30% of solder joints. The majority of passives is still discrete ceramic based and of standard outline. The 0201 passives, which have the smallest body size, are now being used in high volumes for commercial applications. Their market share is rapidly increasing. This is in response to high demand for hand-held products such as cell phones, PDAs (personal digital assistant), global positioning systems (GPS), etc., that require high functionality at reduced cost and size.

All electronic systems continue to be subjected to the trend of added functionality in a shrinking package technology. For the silicon integrated circuits (ICs), this trend is enabled for the most part by the shrinking of feature size. Unfortunately, passive components have not kept up with ICs in this regard. Passive components are not as functionally space efficient as ICs and are seen as one of the major roadblocks in increasing the functional density of electronic systems. Clearly, the need for functional density will force designers to look at creative packaging alternatives. If the historical rate of passive component density continues, by 2010 it is reasonable to expect passive component densities of 20–30 passives/cm2. An alternative to size shrinkage that has gained some popularity is the use of embedded passive devices, where arrays of resistors or capacitors are inserted into a component or a PCB [1]. The inability to create high value embedded devices in a space-efficient manner puts limitations on the amount of integration possible. Also, most embedded advances will continue to suffer, primarily due to component density and tolerance limitations when compared to discrete passives.

In the late 1970s, a typical passive component measured 3.2 mm × 1.6 mm (1206) in size. Ten years later in the 1980s, 0805 passives became the most common with a size of 2.0 mm × 1.25 mm. The end of the millennium saw 0603 passives measuring 1.6 mm × 0.80 mm claiming the largest usage; and 0402 passives at 1.0 mm × 0.50 mm were becoming the most popular size, until recently. The 0201 and 01005 passives, which are the smallest passives in production and evaluation to date, have dimensions of only 0.60 mm × 0.30 mm and 0.4 mm × 0.2 mm, respectively. Compared to 0402s, 0201s are about four times smaller in area and nearly five times lighter, which makes them especially attractive for small portable systems. For example, implementation challenges of the 01005 passive component for use in wireless systems-in-package (SIP) was discussed in a recent publication [1].

The use of 0201 and smaller passive components in products has made the product lighter to handle but more difficult to assemble. This has also reduced the assembly process window considerably and hence the process yield. For this reason, the emphasis of this investigation has been to understand the key parameters influencing the formation of manufacturing defects as well as their impact on interconnect reliability.

Several studies in the past have investigated the influence of various PCB and manufacturing parameters such pad shape, pad dimension, pad spacing, solder mask and non-solder mask defined (SMD and NSMD) pad, board finish, stencil aperture design and reflow process parameters for 0201 assembly. These authors have also discussed techniques for yield enhancements and defect-free assembly process. A 0201 assembly process investigation by Baldwin et al. [2] suggests that static factors such as PCB and stencil design have a much greater effect on the defect rate than dynamic factors such as print processes, pick-and-place parameters and reflow profiles. Wang et al. [3] suggested that round pads performed the best, whereas rectangular pad shape in combination with rectangular aperture size produced the lowest number of defects.

Huang and Yu [4] evaluated the influence of pad design and surface finishes [HASL, OSP, ImAg (IAg)]. It was shown that a square pad with 12 mils (300 μm) dimension and a pad spacing of 9 mils (225 μm) produced the lowest number of defects. The stencil with the square aperture, however, showed clogging whereas the trapezoidal aperture performed better. These authors also found that all three surface finishes yielded similar results. ENIG board finish was also used in another experiment by Wang et al. [5] with lead-free solder paste.

Medernach and Suzuki [6] showed that in a production environment the 6 mil (150 μm) pad spacing produced good results when compared to 4 mil (100 μm) spacing. It was also shown that home plate aperture shape can be used for 4 mil (100 μm) pad spacing. Wang et al. [3] found that the overall solder paste volume on a pad depends upon whether it is SMD or NSMD. Solder paste volume on SMD pads were 20% higher than that on NSMD pads. Other authors [7] show that regardless of process parameters, solder balls predominantly existed on SMD pads.

While investigating the solder paste type Brooks et al. [8] identified that Type 4 (10–25 μm) solder powder performed better for print volume consistency than the Type 3 (20–45 μm) powder. The authors [8] also found that paste printing performance for Type 3 powder was better for 4 mil (100 μm)-thick stencil than 5 mil (125 μm)-thick stencil.

Most literature data concentrate on reducing manufacturing defects to increase yield rather than to provide data on reliability. Only a few investigators have recently presented reliability data for 0201 assembly [9], [10]. For example, cycles-to-failures of assembled 0201 parts fabricated under several design and process conditions were presented in Ref. [9]. The thermal cycle was over the range of −40 to 125 °C with a 20 min duration. The first failure was found to occur between 1500 and 2000 cycles. Shock-and-vibration test was used to verify the solder joint reliability subject to shock and vibration during mishandling or transporting. Huang and Yu [10] performed both mechanical and thermal cycling representative of consumer product. They subjected 0201 assembled boards to a not-disclosed level of sinusoidal vibration for 30 min and shock. No defects were found after the test. They also observed no solder joint failure visually or by electrical test after 1000 thermal cycles performed in the range of 0–100 °C with a ramp rate of 100 °C/min and dwell of 10 min at extremes.

For implementation of 0201, the assembly processes must be evaluated and optimized for several parameters including the following:

  • Pad design and PCB surface finish.

  • Solder paste selection.

  • Stencil design and solder paste print parameters.

  • 0201 placement.

  • Reflow profile for selected solder.

  • Defect characterization.

  • Inspection.

  • Rework.

  • Reliability evaluation.

All the implementation parameters listed above, except for rework [11], were considered in a comprehensive investigation. A large number of test vehicles built for the investigation consist of 2000 NSMD pad layouts oriented horizontally and vertically with four different shapes. The boards were fabricated with five surface finishes. The amount of solder paste was varied by either using different stencil thickness or aperture opening and the paste patterns applied on pads were matched or unmatched. The test vehicles were assembled with resistors and capacitors using three types of solder pastes: lead-free, tin–lead, and anti-tombstoning. After assembly, the test vehicles were inspected for defects including missing parts and tombstones, solder bridging and beads/balls formation. A number of these test vehicles were subjected to isothermal aging at 150 °C and thermal cycling in the range of −55 to 100 °C. This paper discusses findings for the influence of these parameters on 0201 manufacturing quality and defect formation and their effects on the reliability performance evaluated by isothermal aging and thermal cycling.

Section snippets

Design-of-experiment (DOE)

Based on the literature survey, the parameters considered for this experimental investigations were:

  • Four different pad geometries and two pad layouts.

  • Five surface finishes; hot air solder leveling (HASL); organic solderability preservative (OSP); electroless nickel immersion gold (ENIG); immersion silver (ImAg or IAg); and immersion tin (ImSn or ISn).

  • Three solder alloys: tin–lead; tin–lead anti-tombstoning, and lead-free.

  • Two stencil thicknesses: 3 and 4.65 mils (75 and 116.25 μm); three modified

Defect analysis

The assembled test vehicles were inspected for defects using both an optical and X-ray system and defect occurrences were recorded. The defect type and their percentages for various DOE parameters are discussed in detail below.

Conclusions

This study identified a number of key factors pertaining to the stencil, pad design, and solder paste all of which directly control the 0201 assembly defect rate. Fig. 28, Fig. 29, Fig. 30, Fig. 31 summarize the findings.

Important conclusions include the following:

  • Solder beading is the most prominent defect.

  • Tombstoning does not occur for lead-free solder paste.

  • 0201 resistors give higher percentage of solder beading defect when compared to capacitors. On the other hand, capacitors give a

Acknowledgments

Part of the research described in this publication was conducted at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration.

The authors would like to acknowledge the generous support of Metro Circuits, Indium Corporation, and Photostencil. The author S. Manian Ramkumar would like to acknowledge the effort of his graduate assistants Rahul Newasekar who conducted the experimental runs and defect data collection and

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