Integration of an SCR in an active clamp

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Abstract

This paper presents the integration of an SCR into a HV power clamp. For low currents the structure operates in “active clamp” mode and clamps the voltage to a value above the maximum operating voltage. After snapback the structure clamps the voltage to a low value as an SCR.

Introduction

Smart Power Technologies enable designs with a mixture of CMOS logic, low voltage analogue and high voltage driver transistors on one chip (SoC). As a consequence the chip contains multiple voltage domains at different voltage levels, complicating the ESD protection strategy and requiring the availability of a wide variety of ESD protection elements for different voltage ranges. For low voltage protection elements the well-known grounded-gate or gate-coupled nmos can be used. For medium and high voltage protection elements, other concepts have to be applied. High voltage ESD protections suited as supply protections require that their holding voltage is higher than the maximum supply voltage in the application to ensure latch-up immunity. In an alternative way a minimum latch-up (LU) immunity can be guaranteed by ensuring that the snapback current level (It1) is sufficiently high [1].

In this paper a novel high voltage SCR integrated in an active clamp – a hybrid clamp – is presented. The structure has to withstand 1000 pulses 4.5 kV HBM. It has to be in off-state up to 60 V operating voltage and has to clamp the voltage below 80 V during an ESD event. The leakage level has to stay below 10 nA at 60 V at room temperature. A LU immunity of 250 mA has to be guaranteed. The structure has to clamp the voltage above 60 V in the current range from 0 to 250 mA. For higher currents the clamping voltage can be lower. The aim is to find an area efficient alternative for large HV power clamps (Active Clamps) with sizes up to 126,000 μm2. This structure was integrated into AMIS’ I3T80 technology: a 0.35 μm based 80 V HV technology [2].

Section snippets

Active clamps

Fig. 1 shows the schematics of a well-known type of high voltage supply protection element: the “active clamp” including the parasitic bipolar transistor. In general a lateral NDMOS is used as transistor to handle the ESD current in active mode since this type of transistor is very area efficient. A LNDMOS is known to be weak during parasitic transistor turn-on (snapback) [3], [4]. Hence the circuit of Fig. 1 should be designed in such a way that during an ESD event this structure never reaches

Conclusions

A new type of high voltage SCR with tunable trigger current was designed and implemented. The concept is based on an active clamp circuit with a vertical DMOS with an integrated SCR. A significant area reduction compared to an active clamp could be achieved by a dual conduction mode: DMOS conduction in the low current range and SCR conduction in the high current range.

References (7)

  • EIA/JEDEC STANDARD, EIA/JESD78, March...
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  • Duvvury C, Carvajal F, Jones C, Briggs D. Lateral DMOS design for esd robustness. In: Proceedings of the international...
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