NBTI reliability of Ni FUSI/HfSiON gates: Effect of silicide phase
Introduction
Metal gate electrodes are required for the sub-45 nm node to eliminate poly-Si depletion [1] and for better compatibility with high-k gate dielectrics solving issues such as fermi-level pinning (FLP), posed by using conventional poly-Si gates. Ni fully silicided (FUSI) gates have recently, gained attention as possible metal gate electrode candidates for future CMOS technology nodes [2]. Initial work on FUSI gates was centered on Ni mono-silicide (NiSi) [2]. Recently, Ni-rich silicide phases attracted attention as candidates for PMOS devices, due to their higher effective work function (WF) on HfSiON dielectrics, when compared to NiSi gates (Fig. 1) [3]. This difference in WF has been attributed to the difference in pinning behavior with Ni content (see Fig. 1).
It has been argued that the lower WF of NiSi on HfSiON is due to FLP, while this effect is either milder or not present for the Ni-richer silicides. Within the model that correlates FLP to the formation of Hf–Si bonds at the electrode–dielectric interface, the difference in FLP between NiSi and the Ni-richer silicides has been explained in terms of a different density of Hf–Si bonds [4]. The higher Ni content of the Ni-rich silicide phases also poses a reliability concern related to possible diffusion of Ni into the dielectric.
While, initial negative bias temperature instability (NBTI) studies showed no significant degradation for NiSi gates compared to poly-Si gates [2], the NBTI behavior of Ni-rich silicide phases has not been studied yet.
The focus of this work is to investigate the NBTI reliability, when Ni2Si and Ni31Si12 silicides are used as gate electrodes on HfSiON and compare them to NiSi. The study also investigates the influence of increased pre-metal deposition (PMD) temperature and different poly-Si thicknesses and impact of poly-Si etch back on NBTI.
Section snippets
Experimental
The processing sequence is depicted in Fig. 2 and the processing details are given in Table 1 [5]. The gate dielectric consists of 0.8 nm chemical SiO2 as interfacial layer, followed by 2 nm HfSiOx (Si/Hf ratio of 45/55%) deposited by Metallo-Organic Chemical Vapor Deposition (MOCVD). It received a thermal NH3 nitridation at 800 °C for 1 min. All of the devices received a 420 °C 20 min forming gas anneal. They have EOT ∼1.3 nm.
The stress conditions used in the NBTI measurements are elevated
Results and discussion
Fig. 3 shows the threshold voltage shifts (ΔVth) vs. stress time due to NBTI for a given gate voltage VG = −1.6 V.
A large difference is observed in the case of NiSi phase. This difference is due to difference in the initial threshold voltages, in agreement with the lower WF of NiSi. Since NBTI is an electric field dependent phenomenon [7], comparing ΔVth at a given gate voltage may be misleading and result in erroneous interpretations. Fig. 4 shows the ΔVth plotted at a given gate overdrive VG–Vth =
Conclusion
This study shows that there is no intrinsic difference in the NBTI behavior of the different Ni FUSI phases on HfSiON. The NBTI is controlled by the electric field over the gate dielectrics and is independent of the gate electrode material. It is entirely determined by the dielectrics and the dielectric–substrate interface. FUSI itself does not appear to be a limiting factor from the NBTI reliability point of view.
References (7)
IEEE Trans Electron Dev
(2002)IEDM Tech Digest
(2004)Electron Dev Lett
(2006)
Cited by (0)
- 1
Assignee from Texas Instruments at IMEC.