Study of hot-carrier effects on power RF LDMOS device reliability
Introduction
LDMOS is widely used in RF power applications. In the radar field, a crucial issue to tackle with is the reliability of RF LDMOS submitted to RF pulses with high drain-source DC bias for maximum output power under wide temperature range [1]. For this purpose, we designed and implemented an innovative reliability bench able to keep track of all RF powers, voltages and device base-plate temperatures whose values correspond to stress operating conditions [2].
Temperature is a critical parameter, particularly in RF power electronic devices. This element has a considerable influence on reliability and performances [3], [4], can limit the lifetime of semiconductors and consequently plays an essential part in failure mechanisms [3]. For these reasons thermal shocks and cycling conditions are becoming important for RF LDMOS in many applications. Hot carrier induced electrical device parameter degradation is one of the major concerns in device reliability. The electric parameters of MOS transistors are more and more sensitive to boundary defects, to the presence of charges in the gate oxide and at the Si/SiO2 interface [5]. The miniaturisation of MOS transistor (reduction of the channel length and oxide thickness) leads to the presence of higher electric fields, which are the major source of degradation and lifetime reduction of the MOS transistor. Our work methodology consists in characterizing the device before and after ageing on two different benches (reliability bench and thermal bench). Thereafter, we compare the degraded parameters (static, dynamic and RF) according to the applied stress.
Section snippets
Life-test conditions (reliability bench)
Life-tests are run in the working conditions (pulsed RF) using various device base plate temperatures (10 °C, 25 °C and 150 °C) and a high drain-source voltage (44 V) in order to get more power from the device for radar applications. The discrete RF device used for reliability testing is a commercial 10 W telecom dedicated transistor (LG = 0.8 μm) that operates in class-B at saturation. The parameters set for the tests are the following:
Frequency = 2.9 GHz and pulse width/duty
cycle = 500 μs/50%.
Thermal bench and accelerated ageing conditions
In our experiments, the devices are stressed with an applied drain-source voltage VDS of 40 V and a gate-source voltage VGS necessary to obtain a permanent drain-source current IDS less than 20 mA (without self-heating effect), which corresponds to the quiescent current at ambient temperature. The accelerated ageing tests were performed with a THERMONICS T-2820 precision temperature forcing system (PTFS); the system is designed for trouble-free temperature testing of electronic components (for
Comparison and results discussion
Two critical parameters are monitored during ageing tests (RF life-tests). For high power devices working at saturation point, the significant performance parameters concern output power and drain-source current (measured during RF pulse). Measurements were plotted under these two figures of merit and for three different temperature conditions (see Fig. 2, Fig. 3).
The means for each parameter from the 24, 48, 168, 500, 1000 and 1500 h test down-points have been empirically fitted to log curves,
Summary and conclusion
The reliability was reviewed under microwave operating conditions. Then the critical parameters were put forward by linking them to the RF degradations ones (PSAT and IDSS in RF amplification). This study brings new elements to clarify the problems related to hot carriers and impact ionization under operating conditions met by the RF LDMOS.
The TCT and TST seem to be equivalent because they apparently produce the same degradation. The TST cold test seems to induce faster degradation than the hot
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2011, Microelectronics ReliabilityCitation Excerpt :From the equation of Qox [13], Vth increases if the charge induced by trapped carriers Qtrap, is negative because the fixed charge Qf, is constant. From literature, hot electrons are induced by bias and a part of them have enough energy to cross the energy barrier at the interface SiO2/Si [10]. In accordance with the high electric field, the energy of carriers increases, so more hot carriers are able to cross the SiO2/Si energy barrier and are trapped in the gate oxide.
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2020, 2020 26th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2020 - Proceedings