Elsevier

Microelectronics Reliability

Volume 47, Issues 9–11, September–November 2007, Pages 1353-1357
Microelectronics Reliability

Statistical analysis during the reliability simulation

https://doi.org/10.1016/j.microrel.2007.07.079Get rights and content

Abstract

Because of the evolution of electronic circuits reliability toward very low failure rate, statistical analyses through accelerated aging experiments become too expensive. Therefore, the reliability handling is integrated as early as the design phase. This paper proposes a novel methodology to perform reliability simulation taking into account statistical data such as technological dispersions in order to determine the failure-time dispersions induced by these data.

Introduction

In order to reduce design and test costs, the reliability analysis must be done as early as the design cycle of electronic circuits. Consequently, it must be integrated during the design phase. Then, one talks about “design for reliability” (DFR) strategy. The new design flow, taking into account the design for reliability, is depicted in the Fig. 1 [1]. The DFR loop consists in creating a looping reliability simulation phase on the design which integrates, during the phase of design, the study of reliability by electrical simulations. The reliability simulation aims to predict the impact of physical phenomena from elementary component to system electrical characteristics over the operating time.

To design an analog integrated circuit with industrial quality, each elementary component (such as resistances, capacitors, transistors…) must be sized to satisfy the requested nominal electrical specifications on the one hand, and to guarantee that these specifications will be satisfied taking into account the inevitable technological dispersions on the other hand. Therefore, the analog design include a statistical analysis that implies the centering of figures of merit in order to guarantee an optimal yield production. In other words, it is necessary to know the dispersion of suitable (electrical or physical) factors that affect the electrical performances of the device in order to take into account these factors during the dimensioning phase.

Technological dispersions also induce a failure-time dispersion (see Fig. 2). From this point of view, it is necessary to include statistical analysis during the reliability simulation phase, in order to assess the effect of technological dispersions on the circuit or system reliability.

Our previous works consisted in generating a circuit or system aging behavioral model in order to simulate the aging of this circuit or system in operating conditions according to its mission profile [1], [2]. In our study, the behavioral model is described using VHDL-AMS behavioral language.

This paper presents a novel methodology to perform statistical analysis during the reliability simulation phase based on our previous works. The originality of this methodology is the use of a Monte-Carlo method to change the initial values of each behavioral parameter in order to determine the failure-time dispersion of a circuit.

Section snippets

Monte-Carlo method and statistical analysis for analog design

The Monte-Carlo method consists in random sampling the component parameters values of considered models in their tolerance range and then evaluating the considered figure (or figures) of merit. This operation is carried out a great number of times, and the statistical numerical characteristics are finally calculated. According to the precision of the used statistical models, it is possible to carry out a sufficiently reliable Monte-Carlo analysis.

A Monte-Carlo analysis is used by designers in

Statistical simulation method during reliability simulation

Our design for reliability strategy is depicted in the Fig. 3 and is based on a multi-level behavioral modeling approach [1]. After the design phase, this methodology is built up into two steps. First, aging behavioral models are built (see Fig. 4) following the ascending order of abstraction levels on the basis of the architecture and degradation models of the lower levels. During the second step, the system is simulated, taking into account time-dependent, environmental and operating

The circuit

Our methodology is applied to simple current mirror. Its architecture is given by Fig. 5. The input current is 100 μA and the output voltage is 5 V. The load resistance is equal to 1 kΩ. The simple current mirror is described using VHDL-AMS with two NMOS aging behavioral model according to degradations induced by hot carriers injection (HCI). This model is equal to a SPICE model level 2.

The aging behavioral model of MOSFET is based on Hu degradation model for threshold voltage degradation [5]. In

Conclusion

We have proposed a methodology in the context of design for reliability to integrate reliability handling as of the design phase. This methodology consist in performing reliability simulations taking into account statistical data such as technological dispersion. It is based on Monte-Carlo analyses that modify the initial values of transistors behavioral parameters. On the one hand, it allows to determine the effects of technological dispersions on electrical performances at any time of the

References (5)

  • Bestory C, Marc F, Levi H. Multi-Level modeling of hot carrier injection for reliability simulation using VHDL-AMS....
  • Marc F, Mongellaz B, Danto Y. Reliability simulation of electronic circuits with VHDL-AMS. In: Christoph Grimm, editor....
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