Effect of process-induced voids on isothermal fatigue resistance of CSP lead-free solder joints

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Abstract

With the progressive miniaturization of electronic devices, process-induced voids in lead-free solder joints affect the assessment of thermal fatigue resistance. Voids appear randomly in a solder joint, making quantitative evaluation of fatigue life difficult. This study examined the effect of process-induced voids on the thermal fatigue resistance of CSP solder joints. CSP specimens were subjected to isothermal mechanical fatigue tests; specifically, the accelerated thermal cycle test. When a void is small, it has no apparent effect on fatigue life. However, when voids having diameters of at least 30% of solder diameter are located along the crack propagation route, fatigue life is shortened. FEA and Miner’s law for estimation of fatigue life suggest that voids affect not only the crack initiation but also crack propagation. Estimated numbers of cycles to failure agree quantitatively with the experimental results. The effects of the size, location, and number of voids can be extracted by FEA. As voids along the crack path become larger, fatigue life decreases. Moreover, when two voids are located near the corner of a solder joint on the crack path, a 30% decrease in life appears. This result agrees with experimental results reported in several literatures.

Introduction

Process-induced voids in lead-free solder joints have become one of the major categories for the reliability assessment of electronic devices. Voids are often formed during reflow, from entrapped air from solder flux and component surfaces. The evaporation of the solvent in the solder paste or the metallization of components during the fluxing reaction in the reflow process causes the void formation. It has been known that the reflow process and the solder materials are the most important factors for void formation. Their sizes are relatively large; the percentage area of porosity in solder joints may be up to 50% [1], and their impact on the reliability in solder joints for microelectronic devices should be considered. Several researchers have investigated the formation of voids in solder joints [1], [2], [3], [4], but it is difficult to control void formation during the reflow process. Therefore, the reliability assessment of solder joints with voids is important [5], [6], [7], [8], [9]. The reduction in thermal fatigue life in CSP/BGA solder joints has been shown experimentally [5]. However, since voids are formed randomly in solder joints, the effect of voids on fatigue life is ambiguous. Therefore, the mechanism of failure for solder joints with voids and quantitative evaluation remain unclear.

Thermal fatigue life consists of that defined by crack initiation and that defined by crack propagation. The crack initiation can be often evaluated on the basis of the Coffin–Manson law for BGA/CSP solder joints [8], [9], [10], [11], [12], [13], [14]. When a small void is apart from the crack initiation point, the effect of voids on the crack initiation is small. However, the crack often goes through voids and the effect of voids on the fatigue life is different from that in crack initiation. Then, the location and frequency of voids in solder joints is also the factor which affects the failure life. Therefore, an evaluation method of total fatigue life should be established in order to examine the effect of voids. Moreover, it is not easy to control the configuration of voids. Therefore, a lot of experiments with several voids are needed to elucidate the effect of voids on the fatigue life.

This study examines the effect of voids on the fatigue life of lead-free solder joints in CSP packages. Voids in electronic devices can be classified into two cases: several fine-scaled voids at the intermetallic compound (IMC) and large voids in solder joints. In general, the former could affect the interfacial failure due to drop impact, but the effect on the low-cycle fatigue life is likely to be small because these voids are apart from the crack in the solder. Then, the latter could affect the thermal fatigue in solder joints. In this study, the focus was put on the effect of process-induced voids on the thermal fatigue life. CSP specimens with several voids each were subjected to mechanical shear tests as the accelerated thermal cycle test, and the behavior of crack propagation in solder joints was extracted from cross-sectional observation of solder joints during tests. Finite element analysis (FEA) and Palmgren–Miner linear damage hypothesis (Miner’s law) were applied for the quantitative evaluation of crack propagation in solder joints, and the effect of voids on the failure of solder joints was evaluated quantitatively.

Section snippets

Specimen and experimental procedure

Fig. 1 is a schematic illustration of a specimen, consisting of a chip scale package (CSP) and a printed circuit board (PCB). Sn–3Ag–0.5Cu was used as a solder ball. Fig. 2 shows X-ray images of solder joints in the specimen. Several voids were formed in solder joints by controlling temperature conditions during reflow, and their diameter is up to 50% of solder’s diameter. Voids exist on both the CSP and PCB sides, at random positions.

In this study, the isothermal mechanical fatigue test was

FEA models and analysis conditions

In order to quantitatively evaluate the failure strength of solder joints with voids, finite element analysis was performed. Mechanical fatigue tests reveal that the failure cycle of solder joints with voids varies with the relative position between voids and crack path. In this section, FEM analysis is carried out for the quantitative evaluation of the low-cycle fatigue strength of solder joints with voids.

For the evaluation, crack propagation in the solder joint should be simulated. Several

Conclusion

Solder joints with voids were subjected to mechanical fatigue shear tests, and the behavior of crack propagation was examined. Using FEA with crack path algorithm and Miner’s law, the number of cycles to failure of solder was evaluated quantitatively. The obtained results are summarized as follows:

  • (1)

    When void size is small (within 30% of solder diameter), voids have little effect on failure life.

  • (2)

    When a void is located on the crack path, failure life decreases. On the other hand, when a void is

Acknowledgement

The authors gratefully acknowledge support for this research by a grant from METI (Ministry of Economy, Trade and Industry, Japan).

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