The need for multi-scale approaches in Cu/low-k reliability issues
Introduction
As the continuously demand for high performance, multi-functional and small size of micro-electronic products, the complexity of the advanced IC is increasing and feature sizes are decreasing, as indicated in Moore’s law. For the IC technology, the semiconductor industry is focusing on the development to minimize the intrinsic time delay for signal propagation, quantified by the resistance–capacitance (RC) delay [1], [2]. The increasing demands for the electronic performance of the IC wiring have recently driven the replacement of aluminum with copper traces, and of SiO2 film with alternative materials with lower dielectric. The failure modes which are discovered in the Cu/low-k interconnect exhibit the nature of multi-scale behaviour. In this paper, our multi-scale modeling technologies which are developed for understanding the impact on the IC structures, including the interconnect and packaging, will be reviewed.
In the development of Cu/low-k interconnect structures, several issues arise. For the replacement of Al by Cu, the conventional deposition and removement process is migrated to the single/dual damascene process/structure due to chemical characteristics of the copper. The electromigration (EM) mechanism of copper traces is different from the one in aluminum [3], and the EM influence is also size dependent. Low-k materials have been developing from the 1980s [4], and evolved from Fluorine-doped silica glass (FSG), divinylsiloxane bisbenzocyclobutene (BCB)-based SiLK, methyl-silsesquioxane (MSQ) by spin coating, SiOC(H) by CVD/PECVD. The oxide-doped silica glass (OSG) family is preferred by the industries due to the excellent and reliable electronic performance [2], [5] and the compatibility to the currently existing IC back-end process. The k-value can be reduced in two ways: either chemically by replacing oxygen by the methyl groups, H, or OH, or physically by generating porosity within the material [6]. The porosity, and basic building groups of quadri (Q), tri (T), di (D) and mono (M), are shown in Fig. 1 for SiOC:H. Due to its amorphous and porous nature, the low-k material exhibits low mechanical stiffness [7], [6], [5].
Reliability becomes a concern due to the considerably lower strength and higher CTE of the low-k materials [8], [9]. Among the materials of advanced IC back-end structures, the low-k material has a relatively low mechanical stiffness [10], [11]: approximately 5–15 GPa [2], [7], [6]. The delamination between the low-k material and copper barrier layer is often observed after the packaging process and thermal loading. Experiments [10], [6] show that enhancing the Young’s modulus of the low-k material, e.g., by UV radiation, increases the toughness of the critical interfaces, which is mostly due to increasing of the mechanical stiffness. Furthermore, to ensure successful integration of new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with Cu/low-k structures. Although understanding the low-k material and interface within the IC back-end would essentially resolve the mentioned mechanical issues, proper measurement techniques of the mechanical and chemical status at the interface is not well developed at these extremely small scales.
In this paper, we propose to apply to following methods at different length and time scales:
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Continuum theory (e.g., finite element method – FEM): The continuum-based theory has been developed and applied to simulate the system above the micrometer scale. Herein, the continuum theory is used to simulation the mechanical impact of the IC back end structure under the external thermal–mechanical loading.
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Nano-scaled simulation technology (e.g., molecular dynamics – MD): For the development of new low-k material, it is essential to predict the mechanical stiffness and fracture and interfacial characteristics before the material will be synthesized. These results of the nano-scaled simulation will be forwarded as input for the continuum level.
Experience-based design and qualification methods cannot lead to competitive products with faster time-to-market, optimized performance, low costs, and guaranteed quality, robustness, and reliability. Therefore, there is an urgent need to develop and exploit virtual prototyping (VP) methods [12], [13], [14]. The engineer starts by defining key design parameters (geometry, materials, process history, etc.) and their design spaces based on application feasibilities and experience. The problem is then modeled and simulated to determine a certain product performance objectives, such as stress, damages and failure probability, reliability, durability, and dynamic behaviour. With pre-knowledge and proper execution, these simulation supports can be considerably faster, less expensive, and able to provide more insights than physical prototyping and subsequent testing. In general, virtual prototyping involves the evaluation of response functions, based on, and integrated with, advanced simulation models and optimization tools that can predict the product behaviour reliably and efficiently. The ultimate target is to find settings for a number of design parameters that are optimal with respect to the responses.
Section snippets
Continuum-based fracture models
Fracture mechanics theory provides a way to evaluate if an already present (or assumed) crack of given geometry and location in a sample is critical. To this end, the energy release rate, also called crack driving force, as formulated in Griffith’s energy balance, is calculated (e.g. [15]):Here, W is the external work, U is the elastic energy and is the energy required for crack growth, while with a is the crack length and B is the specimen thickness. The left hand side
Typical results from continuum models
Nowadays, continuum-based modeling approaches are widely used in the academia and industry to model for instance the thermal–mechanical impact on the reliability issues of the Cu/low-k interconnect structures.
Mercado et al. [36], [37], [38] used FE models to understand the impact of packaging on chips with Cu/low-k structures. For this purpose, four level finite element simulations covering the range from board level to interconnect structure level was developed. The focus was on the die–attach
Typical results from molecular modeling
The molecular modeling technique is capable of simulating the atomistic characteristic of the system. However, the current limitation of molecular modeling is the huge computation effort needed when increasing the size of the system to realistic dimensions. Theoretically, molecular modeling was established based on inputs from quantum mechanics through the potential functions, see (6). Therefore, it furnishes an excellent bridge between the continuum scale and quantum mechanics.
Theoretically,
Outlook: multi-scale modeling approach
Micro- and nano-electronic components are multi-scale in nature, caused by the huge scale differences of the individual materials and components in these products, as illustrated in Fig. 4 and 13. This is driven by the ongoing miniaturization down to nano-scale (known as the ‘More Moore’ principle) and the increasing functionality diversification (known as the ‘More than Moore’ principle). Consequently, product behaviour is becoming strongly dependent on material behaviour and phenomena at the
Acknowledgements
The authors are grateful to Dr. F. Iacopi (IMEC, Belgium) for sharing her experimental results and experience of the low-k material. The authors also thank the CAA Modeling Cooperation. C. Yuan thanks Prof. B.J. Thijsse (TU Delft, Netherlands) for the modeling technique of atomic structure at interface. O. van der Sluis thanks Marcel van Gils (NXP Nijmegen), Bas van Hal, Ron Peerlings and Marc Geers (TU Eindhoven) for the co-development of the failure modeling methods.
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