Trends of power semiconductor wafer level packaging

doi:10.1016/j.microrel.2009.09.002

Microelectronics Reliability

Volume 50, Issue 4, April 2010, Pages 514-521

https://doi.org/10.1016/j.microrel.2009.09.002 Get rights and content

Abstract

A review of recent advances in power wafer level electronic packaging is presented based on the development of power device integration. The paper covers in more detail how advances in both semiconductor content and power advanced wafer level package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with next generation wafer level power packaging development, the role of modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of wafer level power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.

Introduction

Over the last two decades, power semiconductor technology has made impressive progress, particularly in the increasingly high power density of monolithic, system multiple function and hybrid designs [1], [2], [3], which are the driving forces towards both the monolithic package and three dimensional (3D) power solution with heterogeneous functional integration.

The development of power packages depends on the development of power device integration. Current power devices include the power integrated circuit (IC)s, high voltage IC (HVIC), discrete metal oxide semiconductor field effect transistor (MOSFET), intelligent discrete power device, combined with functional integration and the integration of passive elements. Hybrid integration includes the standard power module and the intelligent power module (IPM) for high power application. Today’s power integration solution has covered multiple functions, which is one of major directions of power wafer level package development.

The trends are going towards wafer level 3D heterogeneous integration with high switching frequency and with reduced or eliminated bulky magnetics and capacitances as well as soft switching technologies for high efficiency and low harmonics [3]. Silicon carbide (SiC) and other wide bandgap (WBG) semiconductor devices will ultimately be important elements for hybrid integration to advance system dynamic characteristics, overload capability, device ruggedness, and thermal and electrical performance [4], [5], [6], [7], [8].

This paper introduces the power wafer level package trends based on above power device development. A review of recent advances in power wafer level electronic packaging which focuses on monolithic power integrations is presented. It covers in more detail how advances in both semiconductor content and advanced wafer level package design and the materials have co-enabled the significant advances in power device capability during recent years. Extrapolating the same trends in representative areas to the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power wafer level semiconductor solutions. Challenges of power wafer level semiconductor packaging in both next generation design and assembly process are presented and discussed.

In addition to the forward looking trends it is important to recognize that the methods for concurrent engineering of these solutions (both the semiconductor content and high performance package capability) are becoming more increasingly dependent on rigorous use of proven multi-physics/FEA tools and techniques for both new power package development and its assembly process. The challenges for modeling of power semiconductor package in new package and assembly process are investigated and discussed.

Section snippets

Challenges of power wafer level semiconductor packaging

Today, providing energy efficient solutions for various products is becoming increasingly important in our world due to limited energy resources and climate change. Especially significant is the fast growth of consumer electronics in both communications and entertainment, industrial power conversion, automotive, and standard power electronics products. Consumer demand for increased mobility with advanced features and for high efficiency energy solutions has paved the way for a variety of new

Wafer level MOSFET compared to regular discrete power package

Table 1 shows the typical development trends of discrete MOSFET package. It gives the representative power transistor package constituent volumetric percentages. As the package develops from Fairchild early DPak (TO252) through SO8 to MOSFET BGA and MOSFET WLCSP, the molding compound decreases as a percentage of volume, until it reaches zero with the MOSFET BGA and WLCSP packages. At the same time the silicon and interconnect metal increases as a percentage of volume. At DPAk level, leadframe

Higher power density at the wafer level

For the voltage range at 5–100 V, there are a wider range of inductive loads handled with a monolithic solution and higher level of functional integration in monolithic solution. The most interesting application is the wafer level integrated system power conversion solution which combines two power switches (the high side and lower side) together with an IC driver. Fig. 7 shows an example of such a wafer level power system on chip. There are also integrated advanced digital control functions for

Trends in wafer level passives

Although the wafer level passives (resistor, capacitor and inductor) in today are only suitable for very low and tiny power, it is possible for them to integrate with low power BCDMOS or other active IC. Integration of active power switches and passives in wafer level can greatly improve the electrical performance and significantly reduce the parasitic effects. For relative larger power products, like buck converter and DrMos with passives, the development is on going. Fig. 10 gives the

Trends in power SIP/3D development

In many power conversion and power management applications, the optimized semiconductor solution is a combination of lateral and vertical conduction devices. This makes a monolithic silicon solution with both power switching (VDMOS/IGBT) and control function (BCDMOS/CMOS IC) impractical. Therefore the Power SIP becomes necessary. Currently there are two major trends in power SIP/3D package development: one is the wafer level CSP bumping on the leadframe to form various stacked die power

Trends in power package modeling

The power package development today is becoming increasingly dependent on rigorous use of proven multi-physics/FEA tools and techniques. Correct use of the modeling tools can definitely save design time and shorten the number of design cycles. The challenge is, can the modeling tool and methodology be ready to support the new trends in the development of new wafer level power package technology? Examples of the challenges include various designs, reliability and assembly modeling which include

Conclusions

The development of wafer level power package is closely related to the development of the power device. For discrete power device, the trends of power wafer level package are towards the smaller pitch, shrink die and package with high current carrying capability for the low voltage application. Moving the VDMOSFET drain to front side is a trend today, which allows the discrete power WL-CSP to be used in all the surface mount applications. The trends of power wafer level IC package are high

Acknowledgments

The support from Fairchild Package Development, Automation Development and Fairchild Salt Lake are greatly appreciated.

References (39)

Y. Liu et al.
3D modeling of electromigration combined with thermal–mechanical effect for IC device and package
Microelectron Reliab
(2008)
Liu Y, Irving S, Luk T, Kinzer D. Trends of power electronic packaging and modeling. In: EPTC 2008, Singapore;...
Sanchez JL et al. Evolution of the classical functional integration towards a 3D heterogeneous functional integration....
Lorenz L. Key power semiconductor devices and development trends. In: physics of semiconductor device. IWPSD 2007. p....
Z.J. Shen et al.
Power semiconductor device for hybrid, electric, and fuel cell vehicles
Proc IEEE
(2007)
A. Emadi et al.
Power electronics and motor drives in electric, hybrid electric and plug-in hybrid electric vehicles
IEEE Trans Indus Electron
(2008)
C. Caramel
The Bi-IGBT: a low losses power structure by IGBT parallel association
Semicond Sci Technol
(2008)
Millan J, Godignon P, Tournier D. Recent developments in SiC power device and related technology. In: Proceedings of...
Wolfgang E, Harder T. Power electronic technology roadmap – a bottom up approach. In: Proceedings of 5th international...
Bolannos MA. Semiconductor IC packaging technology challenges: the next five years. In:...

Desbiens D. Trends in power semiconductor packaging. In: Eurosime 2005, Berlin; 2005...

Zhang K. ENIAC and its strategic research agenda of more than Moore. In: Eurosime 2006, Italy...

Cognetti C. Semiconductor packaging: present and future. In: Eurosime 2006, Italy...

Wolf MJ, Reichl H. From microelectronic packaging to system integration. In: Eurosime 2007, London...

Poupon G. SIP and 3D development. In: Eurosime 2007, London...

Lee R. Development of wafer level packaging processes for 3D multi-flip chip stacking. In: IEEE ED society Maine...

Shimaamoto H. Technical trend of 3D chip stacked MCP/SIP. In: ECTC57 workshop;...

Orii Y, Nishio T. Ultra thin pop technologies using 50μm pitch flip chip C4 interconnection. In: ECTC57 workshop;...

Meyer-Berg G. Future packaging trends. In: Eurosime 2008, Germany...

Cited by (21)

Investigation on drilling blind via of epoxy compound wafer by 532 nm Nd:YVO<inf>4</inf> laser
2017, Journal of Manufacturing Processes
Citation Excerpt :
In recent years, the thriving development of portable electronic products has greatly facilitated the trend of designing related products featuring high density, high performance, lightness, thinness, shortness and smallness parameters. Packaging with a variety of three-dimensional structures has been newly developed and designed so as to meet the needs of items becoming lighter, thinner, shorter, smaller and higher density [1–4]. Wafer level packaging (WLP), which can significantly lower the cost, has gradually gained the attention of related manufacturers.
Polymeric materials designed with macromolecular structures present different levels of absorbance against different laser wavelengths. CO₂ laser is often applied during the drilling blind via of printed circuit boards (PCB) and substrates used for semiconductor packaging since it features speedy processing time, but its high thermal energy easily causes serious substrate warpage and deformation after drilling is completed. Therefore, Nd:YVO₄ laser is selected to create low thermal energy as the tool used in this study. Factors including laser head movement speed, laser beam diameter, laser shot count, laser current and laser frequency control set at three design levels versus 12 sets of experimental parameters, comprise a total of 36 data sets to be taken into consideration. With the assistance of JMP software, a cross analysis is made in order to obtain the optimal set of parameters applicable to drill blind via on epoxy compound wafers. Finally, observations are made to explore the feasibility of applying the optimal set of parameters to drilling blind via on a macromolecular-structured polymeric material.
Stress evolution during thermal cycling of copper/polyimide layered structures
2014, Materials Science in Semiconductor Processing
Citation Excerpt :
Wafer level packaging (WLP) is one of the fast growing segments in semiconductor packaging industry due to the huge demands for faster, smaller, yet less expensive electronic products with high performance and low-cost [1,2]. The redistribution layer (RDL), which re-routes the peripheral I/O layout into a new area array footprint for solder bumping, is an important technology in WLP [1–3]. Polyimide (PI) and electro-chemically deposited (ECD) Cu are often adopted in the RDL serving as dielectric layer and metal trace, respectively.
Polyimide (PI) and electro-chemically deposited (ECD) Cu film structures are widely adopted as redistribution layer (RDL) in wafer level packaging (WLP) and one potential problem with these multi-layered film structures is the stresses and wafer warpage generated in the thermal process. To understand the thermo-mechanical properties of these layered structures, experimental studies on four different multi-layered film structures during the thermal cycling were carried out in this paper, including ECD Cu/Si substrate, ECD Cu/PI/Si substrate, PI/ECD Cu/Si substrate, and PI/ECD Cu/PI/Si substrate. It is observed that the ECD Cu film on Si substrate did not exhibit significant stress relaxation at high temperature, which is very different from the result of previous research on sputtered Cu film. Furthermore, a distinct strain hardening of ECD Cu film during the course of thermal loading was noted. PI film in ECD Cu/PI/Si structure served as an effective stress relief layer at high temperature and this phenomenon was elucidated by employing dynamic mechanical analysis to characterize the viscoelastic properties of PI. However, after cooling to room temperature, the curvature of ECD Cu/PI/Si substrate is bigger than that of ECD Cu/Si substrate as the stresses in the film structures were typically biaxial and uniform at wafer level. It is also found that the PI passivation layer had little influence on the thermal behavior of Cu film due to its low modulus.
Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking
2011, Microelectronics Reliability
Citation Excerpt :
Recently, electronic devices tend to be light in weight, and have high performance with low power consumption and low prices. In order to satisfy this tendency, these devices require miniaturization with respect to their packaging technology [1]. Three-dimensional (3-D) chip stacking is a popular candidate to meet such miniaturization needs.
The reduction of defects and high-speed copper filling into a through-silicon-via (TSV) for the three-dimensional stacking of Si chips were investigated. The via, with a diameter and depth of 30 μm and 60 μm, respectively, was prepared on a Si wafer by a deep reactive ion etching (DRIE) process. SiO₂, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a 3-step periodic-pulse-reverse (PPR) current waveform was suggested for electroplating. The 3-step PPR consisted of low, medium and high current densities for the 1st, 2nd and 3rd steps, respectively. After Cu filling, in order to estimate defects in the Cu-filling, the via was cross-sectioned and observed by field emission scanning electron microscopy (FE-SEM), and also an X-ray radiographic test was performed for non-destructive inspection. The experimental results showed the via was fully filled without a serious defect by the 3-step PPR process after 80 min of plating, specifically, by current densities of −1.24, −3.22, and −9.89 mA/cm² (1st/2nd/3rd step, respectively). The 3-step PPR filling was a kind of bottom-up filling process of Cu into the via, and it was effective for Cu filling in a short time. Defects, like voids in the Cu-filled TSV, were identified by the X-ray radiographic test, which can be useful for ensuring the reliability of a fragile thin Si wafer for 3D packaging.
Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging
2023, Advancing Microelectronics
Unraveling the Heterogeneity of Epoxy-amine Networks by Introducing Dynamic Covalent Bonds
2023, Chinese Journal of Polymer Science (English Edition)
Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging
2023, 24th European Microelectronics and Packaging Conference, EMPC 2023

View all citing articles on Scopus

View full text

Trends of power semiconductor wafer level packaging

Abstract

Introduction

Section snippets

Challenges of power wafer level semiconductor packaging

Wafer level MOSFET compared to regular discrete power package

Higher power density at the wafer level

Trends in wafer level passives

Trends in power SIP/3D development

Trends in power package modeling

Conclusions

Acknowledgments

Microelectron Reliab

Power semiconductor device for hybrid, electric, and fuel cell vehicles

Proc IEEE

Power electronics and motor drives in electric, hybrid electric and plug-in hybrid electric vehicles

IEEE Trans Indus Electron

The Bi-IGBT: a low losses power structure by IGBT parallel association

Semicond Sci Technol