Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

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Abstract

A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-μm CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by simulation and experimental results with operating speed up to 133 MHz for PCI-X compatible applications.

Introduction

With rapid development of complementary-metal-oxide-semiconductor (CMOS) techniques, the transistor dimension and core supply voltage have been continually scaled down to reduce chip area, to increase operating speed, and to reduce power consumption. Nonetheless, the scaled-down transistors also have the limitation of lower maximum tolerable voltage across the transistor terminals (drain, source, gate, and bulk) under vulnerable circuit operating conditions for lifetime concern. In the mixed-voltage I/O buffers, that interface the high-VDD signal environment of the old I/O specifications to low-VDD environment for low power consumption of core circuits, the voltages across transistor terminals should be managed carefully to overcome reliability problems, such as gate-oxide overstress [1], [2], hot-carrier degradation [3], [4], [5], [6], [7], [8], [9], [10], and the undesired circuit leakage paths (for the conduction of the parasitic drain-to-well pn-junction diode in the main pull-up PMOS device) [11], [12], [14].

The expected normal lifetime for IC products is generally specified as 5–10 years, which will be affected by different processes and overstress conditions. To ensure the circuits at least alive after continually overstress under certain worst-case circuit operating condition [13], transistors operating within 1–1.1 times of normal supply voltage in the I/O or driver circuits become a practical and common design principle [13], [14], [15]. Degradations caused by hot carriers and gate-oxide overstress are actually time dependent issues as discussed in [16], [17], [18], [19], which are also functions of the probability for the happening of overstress condition during circuit operations. When the drain voltage of NMOS device is larger than its gate voltage (for the overstress condition in the following circuits under discussion), the drain avalanche hot carrier injection (DAHC) becomes an important mechanism [5]. For digital logic circuits, AC stress problems due to hot-carrier degradation and overstress in transition are also important to lifetime concern since barely transistors under turn-on state were with large DC drain-to-source stress on them [20], [21]. For ensuring IC products to meet normal lifetime expectation, reliability problems in both of steady state and transition period should be considered.

The I/O circuits of prior arts those attempted to avoid reliability problems due to gate-oxide overstress and hot-carrier degradation have been reported in [13], [14] and [22], [23], [24], [25], [26]. To realize the I/O buffer with 1.8/3.3/5-V mix-voltage tolerance without gate-oxide reliability issue, one prior design implemented with 3.3-V devices in a 0.35-μm CMOS process was reported in [22]. Besides, the dual-oxide (thick-oxide and thin-oxide) process [23], [24], [25] was also provided by foundry, that can be used to prevent the reliability anxiety in mixed-voltage interface against gate-oxide overstress and hot-carrier degradation. Two kinds of devices (such as 1-V and 2.5-V transistors) were also adapted to output 3.3-V signals without aforementioned reliability anxiety [26]. However, the chip fabrication cost is also increased by using the dual-oxide process with the additional mask layer and the corresponding process steps. In [14], an I/O buffer implemented with only thin-oxide devices was reported. However, some overstress problems still exist in the prior design [14] under some specified transitions, which will be further discussed in Section 2 of this paper.

To alleviate the aforementioned reliability problems during both steady state and transition period in the mixed-voltage I/O buffer with only 1xVDD devices, a new 2xVDD-tolerant I/O buffer with novel transmitting circuit and new gate control circuit is proposed in this work [27] and successfully verified in a 0.13-μm CMOS process.

Section snippets

Hot-carrier degradation and gate-oxide reliability in the prior I/O circuits realized with thin-oxide devices

A conventional mixed-voltage I/O buffer with the gate-tracking circuit and the dynamic n-well bias circuit is shown in Fig. 1 [14]. The limitations of voltage difference within 1.1xVDD across the terminals of each transistor can be satisfied by the circuit in Fig. 1 under steady state. However, during the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the Vds of transistors MN0 and MN3 will be much higher than VDD. The drain-to-source voltages of MN0 or MN3

New proposed mixed-voltage I/O buffer

The new proposed 2xVDD-tolerant I/O buffer realized with only 1xVDD devices to prevent transistors against gate-oxide reliability and hot-carrier degradation is shown in Fig. 8, which keeps the major design advantages of the prior arts with three additional new modifications. The design concepts of the major parts in this new proposed I/O buffer are introduced in the following.

Simulated waveforms for steady state operation and verification to new modifications

The simulated results of the new proposed 2xVDD-tolerant I/O buffer to prevent hot-carrier degradation and gate-oxide reliability have been verified by the HSPICE simulation in a 0.13-μm CMOS BSIM3 model (V3.2) with VDD of 1.2 V. The sizes for transistors are listed in Table 3. Figs. 9 and 10 show the simulated waveforms of the new proposed 2xVDD-tolerant I/O buffer well operating with speed of 150 MHz in the receive mode and transmit mode, respectively. As shown in Fig. 9, when new proposed

Experimental results

The new proposed mixed-voltage 2xVDD-tolerant I/O buffer has been fabricated in a 0.13-μm 1.2-V CMOS process with only thin-oxide (1.2-V) devices. The layout-top-view and the die photograph of test chip are shown in Fig. 17a and b with the corresponding circuit blocks, including VDD power cell, I/O circuit, Dout pad, EN pad, Din pad, and VSS power cell.

The signals appear in the pins of fabricated chip are measured by the oscilloscope with the sampling rate of 5 GS/s and a bandwidth of 500 MHz.

Conclusion

A new 2xVDD-tolerant I/O buffer against gate-oxide overstress and hot-carrier degradation has been successfully verified in a 0.13-μm 1.2-V CMOS process with only thin-oxide devices. The gate-to-source, gate-to-drain, and drain-to-source voltages of the transistors in the new proposed 2xVDD-tolerant I/O buffer can be kept within the normal operating voltage (VDD) with simulated verification. The new proposed 2xVDD-tolerant I/O buffer can receive 1.2-V/2.5-V input signals or transmit 1.2-V

Acknowledgements

This work was partially supported by “Aim for the Top University Plan” of the National Chiao-Tung University and Ministry of Education, Taiwan, ROC; and partially supported by National Science Council (NSC), Taiwan, under Contract of NSC 97-2220-E-009-046.

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