On the importance of the V_g,max–V_th parameter on LTPS TFT stressing behavior

Abstract

In this work we point out the importance of the device parameter V_g,max–V_th (the difference between the gate voltage at maximum transconductance and the threshold voltage obtained from linear extrapolation method) for LTPS TFTs under dc stress. The evolution of this parameter with stress time is monitored for the first time, along with the other typical device parameters (V_th, G_m,max, S) in order to further clarify the nature of the traps generated. In the first dc stress case considered, we observed very different S degradation of the two samples, but very similar G_m,max degradation, as well as similar V_g,max–V_th evolution. Therefore, G_m,max evolution with stress time was found to be related more strongly to tail state generation, probed through V_g,max–V_th, and not to midgap trap generation, probed through S. In the second case, no midgap state generation is observed, but only severe tail state generation. Hence, the nature of the created defects and the reason for the significant G_m,max reduction could only be probed through the observation of V_g,max–V_th, a parameter not utilized until now. Finally, stressing both n- and p-channel devices, we are able to explain the much more intense G_m,max degradation observed for n-channel devices, associating it to the larger tail state generation in n-channel TFTs, also pointed by V_g,max–V_th evolution with stress.

Introduction

Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) are essential for large area electronics, VLSI technology and high performance flat panel display applications [1]. The primary advantage of poly-silicon TFTs over a:Si ones is their higher field-effect mobility and consequently higher drive current. With the recent poly-silicon crystallization process breakthroughs, using various excimer laser anneal (ELA) methods such as sequential lateral solidification (SLS), the TFT performance has substantially increased [2], [3], [4], [5], [6]. The several variations of the SLS technique allow the manufacturing of poly-silicon films with excellent intragrain quality and grains of different geometry. However, high TFT reliability should also be achieved for the fabrication of commercial products to be possible. Unfortunately, the degradation mechanisms of advanced LTPS TFTs have not yet been fully clarified, not allowing us to positively identify the origin and nature of the defects created through device stressing [7], [8]. Such information would be invaluable to the LTPS TFT industry, since it would provide input on the factors degrading the TFTs and therefore help optimize their performance through time and their operational lifetime.

In this work, we explore the potential of a newly introduced electrical characterization parameter, namely V_g,max–V_th, proved to reflect the density of poly-silicon traps density particularly near the edge of the band gap [9], also known as tail states, as a means to distinguish the defects created by the stress. This way we suggest for the first time the importance of using the parameter V_g,max–V_th for stressing experiments and propose its use along with the ones already monitored during stress (V_th, S, G_m,max) in order to specify the nature and origin of the created defects.