On the importance of the Vg,max–Vth parameter on LTPS TFT stressing behavior
Introduction
Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) are essential for large area electronics, VLSI technology and high performance flat panel display applications [1]. The primary advantage of poly-silicon TFTs over a:Si ones is their higher field-effect mobility and consequently higher drive current. With the recent poly-silicon crystallization process breakthroughs, using various excimer laser anneal (ELA) methods such as sequential lateral solidification (SLS), the TFT performance has substantially increased [2], [3], [4], [5], [6]. The several variations of the SLS technique allow the manufacturing of poly-silicon films with excellent intragrain quality and grains of different geometry. However, high TFT reliability should also be achieved for the fabrication of commercial products to be possible. Unfortunately, the degradation mechanisms of advanced LTPS TFTs have not yet been fully clarified, not allowing us to positively identify the origin and nature of the defects created through device stressing [7], [8]. Such information would be invaluable to the LTPS TFT industry, since it would provide input on the factors degrading the TFTs and therefore help optimize their performance through time and their operational lifetime.
In this work, we explore the potential of a newly introduced electrical characterization parameter, namely Vg,max–Vth, proved to reflect the density of poly-silicon traps density particularly near the edge of the band gap [9], also known as tail states, as a means to distinguish the defects created by the stress. This way we suggest for the first time the importance of using the parameter Vg,max–Vth for stressing experiments and propose its use along with the ones already monitored during stress (Vth, S, Gm,max) in order to specify the nature and origin of the created defects.
Section snippets
Experimental
The TFTs studied were fabricated in 50 nm thick poly-silicon films, formed by two different SLS ELA crystallization techniques: M × N [10], [11] and location control crystallization [12], with each one yielding a different grain geometry and poly-Si microstructural characteristics. For the M × N technique, in particular, two variations were examined: M × N#8 yielding larger domain sizes and “advanced” M × N (M × Nadv) yielding smaller domain sizes. The above crystallization techniques were used
Results and discussion
The first crystallization technology studied was the M × N technique, applying Vg,stress = 5 V, Vd,stress = 10 V for the M × N#8 variation and Vg,stress = 4 V, Vd,stress = 8 V for the M × Nadv variation, since these devices proved to be more sensitive. The fact that the M × Nadv sample is more sensitive to stress could be attributed to the smaller crystal domain sizes obtained from this procedure. Smaller domain sizes result in more protrusions of the poly-silicon film in the gate oxide, therefore more points of
Conclusions
Advanced SLS ELA TFT degradation behavior, under dc stress, is investigated, utilizing for the first time the evolution of the parameter Vg,max–Vth in order to further clarify the nature of the traps generated. In the first dc stress case considered, the Gm,max degradation was found to be related more strongly to tail state generation, probed through Vg,max–Vth, and not to midgap trap generation, probed through S. In the second case, no midgap state generation is observed, but only severe tail
Acknowledgement
The authors acknowledge financial support through the research project PENED 3ED550, administered by the Greek General Secretariat for Research and Technology.
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