Predictive modeling of board level shock-impact reliability of the HVQFN-family

doi:10.1016/j.microrel.2009.10.015

Microelectronics Reliability

Volume 50, Issue 2, February 2010, Pages 228-234

https://doi.org/10.1016/j.microrel.2009.10.015 Get rights and content

Abstract

A semi-empirical model is derived to predict the board level drop-impact lifetime of HVQFN-packages soldered on a printed circuit board. The strain that evolves in the soldered interconnections is evaluated by a finite element model and related to the experimentally determined lifetime. The result is a power law and it is compared to literature data. In addition, a measure for the strain on the board is obtained analytically and compared with the experimental data. Here, too, dependence in the form of a power law is found. The combination of both results strongly suggests a near-linear relationship between the strain in the solder and the strain in the board.

Introduction

In the past decade, quad flat no-lead (QFN), or micro-lead frame (MLF), packages have been developed for electronics applications. As they do not have leads they occupy a relatively small area, and their low solder height results in a low self-inductance. The large heat sink gives them a very good thermal performance. The version with a very low building height is usually called HVQFN: heat sink very thin quad flat-pack no leads. But nevertheless, until recently, the board level reliability of QFN- and HVQFN-components has received little attention. Particularly the low stand-off of these packages may be a concern.

Board level reliability tests consume both a lot of time and money. Still, they are very relevant to the development of electronic packages. A methodology that must allow for predictive simulation techniques for board level reliability is under development. According to this methodology, one can select a few packages from an entire family for testing, fit the simulation to the experimental data, and use the result to estimate the lifetime of the other members by interpolation. Earlier investigations were done by using this approach to thermal cycle stress loading of BGA-packages [1] and HVQFN-packages [2]. Something similar was also done for ultra chip scale packages [3].

The past decade has seen an increasing number of publications addressing the effect of impact loading on electronic assemblies. To restrict ourselves to the more recent ones, Wong et al. [4] presented an analytical and numerical model, with qualitative material properties. Various approaches for the numerical model were compared. The use of a high-speed camera to determine acceleration and strain was demonstrated by Tee et al. [5]. The focus was on finite element analyses. This has resulted in a predictive lifetime model. At the University of Limerick, Heaslip et al. studied the distribution of failure sites of BGA-assemblies. Analytical and numerical modeling of the peel stress was compared to material properties [6]. Chai et al. considered the assembly as a plate bending under impact [7]. Basic inputs for the modeling were the acceleration and the resulting strain. As an alternative to impact testing, high-speed bending was used for a detailed study of the failure mode and crack propagation [8]. Marjamäki et al. and Mattila et al. reported on using vibration loading with high amplitude to simulate the impact test [9], [10].

In addition to the papers referenced above, work has been published specifically on the mechanical impact performance of QFN-packages. Chai et al. reported results of a shock test according to the JEDEC test standard [11]. This was done on QFN-packages mounted with SnPb- or SAC-solder on two-layer boards [7]. The difference between these boards and the recommended (JEDEC) boards, with respect to the flexural modulus and the density, was checked. The JEDEC boards’ values were 24.8 GPa and 2039 kg/m³, whereas the two-layer boards’ values were 21.0 GPa and 1899 kg/m³. Chong et al. studied amongst others VQFN48-packages that were assembled with eutectic SnPb-solder and SAC405-solder [12], [13]. The boards had a dimension of 200 × 150 mm². Prior to the drop test they received a thermal cycling stress. The clamping was along the long edge of the boards – this is not according to the JEDEC standard. Birzer et al. report on testing QFN48-packages on JEDEC-boards [14]. One has made these with Cu-track widths of 75 μm and 150 μm where the daisy chain is made on the top layer, and a version where the daisy chain is made through the vias-in-pad. The many variations in these experiments make it clear that a comparison of the results with our own data will be difficult.

In this paper experiments and simulations on the drop-impact test on HVQFN-packages will be combined for the first time. We will discuss a set of experimental data of various HVQFN-packages subjected to such loading. A numerical model was built to calculate the solder strain, and used to interpret the results. In addition, the board strain is estimated from an analytical model, and compared to the numerical model. The outcome of the experimental and the modeling results are compared to literature data. This investigation forms part of a coherent set of experiments and modeling studies on board level reliability.

Section snippets

Experiments and simulations

HVQFN-packages with various numbers of leads were assembled on printed circuit boards with a layout that was according to the JEDEC test standard [11], except that in this case they were equipped with four Cu-layers (each 35 μm in thickness) and that they did not have vias. As mentioned in the introduction, this does not appear to severely affect the relevant board properties [7]. The board finish was Cu-OSP. Soldering was done in a reflow oven using lead free soldering paste of SAC305

Results

The measured acceleration (see Fig. 3) shows the main shock pulse and some additional features. These additional features are due to higher order eigen frequencies, in particular the fifth at around 700 Hz. They have a second order impact on the durability of the interconnection.

The failure distributions are given in Fig. 7. In Table 2, the results of the statistical analysis are compiled.

One board with medium-size packages was put through 95 drops; at that point, only two products survived.

Discussion

As we intend to make a semi-predictive model, one of the first things to do is to check for the failure mode and mechanism. From the failure analysis it is clear that two modes dominate: solder joint cracks and intermetallic-layer cracks. Other failure modes such as breaking of the Cu-tracks were not found. In some cases cracks in the solder and the intermetallic layers appear in one and the same interconnection (see Fig. 9a). This is in line with many observations in literature, where

Conclusions

In this study the board level drop-impact lifetime of HVQFN-packages was determined experimentally. A semi-empirical model that is intended to help estimate the solder joint reliability was developed by means of finite element calculations. The results can be summarized with the following conclusions.

–
A fatigue-based model is applied to describe a mixture of that with overstress-induced failure behavior. The authors admit that this is unusual, but in practice the model agrees with the

Acknowledgements

The authors thank J. Caers, R. Engelen, M. Jansen, I. Lemmens and W. Vogels (Philips) and F. Kessels (NXP) for their valuable advice and support.

References (22)

J. de Vries et al.
On the difference between thermal cycling and thermal shock testing for board level reliability of soldered interconnections
Microelectron Reliab
(2007)
J. de Vries et al.
Solder-joint reliability of HVQFN-packages subjected to thermal cycling
Microelectron Reliab
(2009)
X.J. Zhao et al.
Solders fatigue prediction using interfacial boundary volume criterion
J Electron Packag
(2003)
T.Y. Tee et al.
Impact life prediction modeling of TFBGA packages under board level drop test
Microelectron Reliab
(2004)
D.Y.R. Chong et al.
Drop impact reliability testing for lead-free and lead-based soldered IC packages
Microelectron Reliab
(2006)
S. Wiese et al.
Time-independent elastic–plastic behaviour of solder materials
Microelectron Reliab
(2004)
E.H. Wong et al.
Drop impact test – mechanics & physics of failure
Proc EPTC
(2002)
G.M. Heaslip et al.
A stress-life methodology for ball grid array lead-free and tin–lead solder interconnects under impact conditions
Proc EuroSime
(2005)
T.C. Chai et al.
Board level drop test reliability of IC packages
Proc ECTC
(2005)
S.K.W. Seah et al.
Failure mechanisms of interconnections in drop impact
Proc ECTC
(2005)

P. Marjamäki et al.

A comparative study of the failure mechanisms encountered in drop and large amplitude vibration tests

Proc ECTC

(2006)

Cited by (2)

The reliability of component boards studied with different shock impact repetition frequencies
2012, Microelectronics Reliability
Citation Excerpt :
Again, the same failure modes were observed, regardless of the impact repetition frequency used. Similar types of failures have also been observed earlier [19]. Since the same failure modes were observed and the impact repetition frequency is the only difference causing the different average number of impacts-to-failure in Fig. 7, the root cause of the different lifetimes must be related to events that take place between the successive impacts.
As a result of the ever-shortening time to market of new electronic products there is a clear need to make the currently employed reliability assessment procedures more efficient. However, while trying to achieve these cost savings it is important to pay attention to how much reliability tests can be accelerated without producing misleading lifetime statistics or irrelevant failure modes and mechanisms. Therefore, the primary objective of this work was to clarify the effects of impact repetition frequency on the lifetime and failure mechanisms of electronic component boards. The reliability assessments were conducted with four package types (BGA288, BGA144, QFN72, and μSMD36) with the intention of including different package dimensions and interconnection shapes and sizes in the scope of evaluation. Three shock impact repetition frequencies (0.01 Hz, 0.1 Hz, and 1.6 Hz) were used to study the sensitivity of their lifetime to the time between the shock impacts. The results showed that the impact repetition frequency has a significant effect on the average lifetime of the studied packages: the average number of impacts-to-failure increased with increased impact repetition frequency. A change in the impact repetition frequency did not, however, change the primary failure mode and the failure mechanism. In order to explain this observation, the formation of residual stresses in the solder interconnections from shock impacts and their relaxation during the time between the shock impacts were evaluated by employing FEM, which showed that at room temperature the stress relaxation by creep of solder is significant even at less than 10 s time frame. The effect of the stress relaxation on the lifetime of the component boards was studied experimentally by repeating the impact tests at elevated temperature with the intention of influencing rate of stress relaxation. The results showed that the relaxation of the residual stresses has a significant effect on the component boards shock reliability (at less than 1% risk level). The results presented in this paper indicate that the impact repetition frequency should be taken into account, especially when reliability assessments are being carried out with different testers, since the interval between the shock impacts varies from one test system to another.
Simulation Study of the High-G Drop Impact Testing of Microelectronic Packaging Products
2021, InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM

View full text

Predictive modeling of board level shock-impact reliability of the HVQFN-family

Abstract

Introduction

Section snippets

Experiments and simulations

Results

Discussion

Conclusions

Acknowledgements

Microelectron Reliab

Microelectron Reliab

J Electron Packag

Microelectron Reliab

Microelectron Reliab

Microelectron Reliab

Drop impact test – mechanics & physics of failure

Proc EPTC

A stress-life methodology for ball grid array lead-free and tin–lead solder interconnects under impact conditions

Proc EuroSime

Board level drop test reliability of IC packages

Proc ECTC

Failure mechanisms of interconnections in drop impact

Proc ECTC

A comparative study of the failure mechanisms encountered in drop and large amplitude vibration tests

Proc ECTC