Electrical characteristics and reliability properties of metal–oxide–semiconductor capacitors with HfZrLaO gate dielectrics

https://doi.org/10.1016/j.microrel.2010.01.014Get rights and content

Abstract

Metal–oxide–semiconductor (MOS) capacitors incorporating atomic-layer-deposition (ALD) HfZrLaO high-κ gate dielectric were fabricated and investigated. The equivalent oxide thickness (EOT) is 0.68 nm and the gate leakage current density (Jg) is only 9.3 × 10−1 A/cm2. The time-dependence dielectric breakdown (TDDB) behavior agrees with the percolation model, and the TDDB characteristics are consistent with the thermochemical E-model for lifetime projection. The experimental results show that the Weibull slopes are almost independent of capacitor area and stress conditions. The field acceleration parameter (γ) and activation energyH0) are determined around 5.9–7.0 cm/MV and 0.54–0.60 eV, respectively. At 85 °C, the maximum voltage projected for 10-years TDDB lifetime is 1.87 V.

Introduction

In the literatures, hafnium dioxide (HfO2) gate dielectrics have encountered the following process integration related problems: (1) low crystallization temperature (∼500 °C); (2) high threshold voltages (VT) for n- and p-MOSFETs, which is due to the so-called Fermi-level pinning (FLP) [1], [2] or flat-band voltage (VFB) rolloff [3], [4]. Researchers have introduced Si, N, Al, or Ta into HfO2 thin films in an attempt to increase the crystallization temperature and solve unacceptable VT issue [5], [6], [7], [8]. Although the above additives can improve crystallization temperature and obtain low VT for metal–oxide–semiconductor field-effect-transistors (MOSFETs), the dielectric constants and the barrier heights at gate/dielectric or dielectric/substrate decrease significantly compared to pure HfO2 [9].

More recently, rare earth metal La (lanthanum) incorporation into HfO2 gate dielectrics has been successfully demonstrated to achieve desired device characteristics with low VT, increased crystallization temperature without degradation of dielectric constant, relatively high barrier height at metal gate and high-κ gate dielectric interface, and improved positive bias temperature instability (PBTI) reliability [10], [11], [12], [13], [14]. Another approach to solve the HfO2 problems is to adding Zr (zirconium). It was reported that HfZrO (hafnium zirconate) has lower n-channel MOSFETs VT, higher transconductance, lower charge trapping density and interface trap density, higher drive current, reduced capacitance–voltage (CV) hysteresis, superior wafer-level thickness uniformity, and improved PBTI reliability [15], [16], [17].

In order to obtain a better gate oxide dielectric, to combine the additives of La and Zr is a worthy attempt. Therefore, in this study we reveal a process for making HfZrLaO thin films and then investigate their electrical characteristics. In addition, time-dependent-dielectric breakdown (TDDB) reliability is one major concern in advanced technology. It has not yet been fully understood for Hf-based high-κ dielectrics, especially for HfZrLaO gate dielectrics. Hence, this work also investigates the TDDB characteristics of HfZrLaO high-κ/metal gate stack structures.

Section snippets

Experiment

P-type (1 0 0) Si wafers were used as the starting substrates. After the standard cleaning procedures, a 2-nm HfZrO thin film was first deposited by using atomic-layer-deposition (ALD), followed by 1-nm ALD LaO capping layer. A 10-nm TaC metal gate was subsequently deposited by physical vapor deposition (PVD) as the gate electrode. Finally, a post-metal-anneal (PMA) was done at 420 °C in forming gas for 30 min.

The areas of the MOS capacitors range from 9.0 × 10−7 to 3.0 × 10−3 cm2. Based on

Electrical characteristics of MOS capacitors with HfZrLaO gate dielectric

The inset in Fig. 1 illustrates the stacking of TaC/LaO/HfZrO/p-Si capacitors in this article. Based on process sequence, however, it is believed that mutual diffusion of LaO and HfZrO have occurred such that certain form of mixing and bonding is generated after annealing [13], [14]. Therefore, the gate dielectric is name HfZrLaO hereafter although it is not accurately correct stoichiometrically. Fig. 1 shows the high-frequency (100 kHz) and simulated CV characteristics of MOS capacitor with

Conclusions

In summary, MOS capacitors with novel HfZrLaO gate dielectrics were fabricated and extensively investigated. The breakdown behavior agrees with the percolation model, and the TDDB characteristics are consistent with the thermochemical E-model for lifetime projection. It was observed that the Weibull slopes were almost independent of capacitor area, stress voltage and temperature. The γ, ΔH0, ΔH0, and p0 are determined about 5.9–7.0 cm/MV, 0.54–0.60 eV, 2.16 eV, and 2.86 eÅ, respectively. At 85 °C,

Acknowledgements

The authors would like to acknowledge Prof. S.Y. Chen and Prof. H.S. Huang at NTUT and Dr. L.W. Cheng at UMC for informative discussions.

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