Impact of strain on hot electron reliability of dual-band power amplifier and integrated LNA-mixer RF performances

https://doi.org/10.1016/j.microrel.2010.02.019Get rights and content

Abstract

Channel hot-electron-induced degradation on strained MOSFETs is examined experimentally. BSIM stressed model parameters are extracted from measurement and used in Cadence SpectreRF simulation to study the impact of channel hot electron stress on dual-band class-E power amplifier and integrated low-noise amplifier-mixer RF performances. Channel hot electron effect decreases power efficiency of dual-band class-E power amplifier and increases the noise figure of low-noise amplifier-mixer combined circuit.

Introduction

With aggressive MOSFET scaling toward the 45 nm technology node and beyond, reliability issues such as channel hot carrier injection (HCI) resulting from high electric field near the drain edge becomes increasingly important. It is well known that HCI-induced interface states and oxide trap charge degrades MOS transistor performances [1], [2]. Chen et al. [3] illustrated that channel hot electrons, not carriers injected into the gate oxide, are primarily responsible for interface trap generation for hot electron stress. For MOS transistors today the maximum channel hot electron degradation occurs at VGS = VDS [4]. The threshold voltage shift by HCI follows the power law characteristic with an exponent around 1/2. In addition, hot electron lifetime decreases with increasing drain voltage and temperature [5] and drain current degradation is less under AC (dynamic) stress [6]. Recently, degeneration of CMOS power cells after hot-carrier stress and load mismatch has been evaluated [7]. By imposing RF stresses on the output terminal under different input power levels, the average energy of each carrier under larger input power is much higher than that from DC stress. However, the HCI degradation is reduced at low input RF power level.

In the past few years, RF circuit performances subjected to hot electron effect have been extensively studied [8], [9], [10], [11], [12], [13], [14]. For example, hot electron stress increases noise figure of low noise amplifiers (LNAs) [8], [9], decreases power efficiency of power amplifiers [10], [11], increases phase noise of oscillators [12], [13], and increase nose figure of mixer [14]. However, the impact of device strain on the hot electron reliability for dual-band power amplifier and LNA-mixer combination circuit has not been examined.

In this paper, the MOS transistors with high tensile contact etch stop layer (CESL) of 700 Å and SiN layer of 380 Å subjected to hot electron stress are examined experimentally. BSIM model parameters are extracted before and after hot electron degradation at various stress time points. The stress model parameters are used in Cadence SpectreRF simulation to investigate the impact of hot carrier reliability on the dual-band class-E power amplifier and LNA-mixer RF circuit performances.

Section snippets

Strained MOSFETs

As the gate length of MOS transistors scales to the nanometer regime, high channel mobility is required to further improve device driving current capability. The use of strain techniques [15], [16], [17], [18], [19], [20] such as relaxed SiGe layer or epitaxial SiGe in the source and drain regions and contact etch stop layer in the gate to improve channel mobility have been popular. Without accompanying the increase of process steps, changing the thickness of CESL to control the tensile and

Dual-band class-E power amplifier and LNA-mixer schematics

Power amplifier is an essential circuit element for wireless communications. In several power amplifiers, the switched-mode class-E tuned power amplifiers [21], [22] with a shunt capacitor have found widespread application due to their design simplicity and high power efficiency. Concurrent dual-band operation is beneficial to reduce the number of circuit components in modern mobile systems requiring two frequency bands. The use of concurrent right- and left-handed transmission lines [23]

Results and discussion

The dual-band class-E power amplifier shown in Fig. 5 is evaluated. The class-E power amplifier has the inductors L1 = 2.635 nH, L2 = 5 nH, capacitors C1 = 20 pF, C2 = 20 pF, and the supply voltage of 1.5 V. The MOS transistor of the power amplifier is biased at 1 V. The sinusoidal input source signal is chosen at 800 MHz and 2.1 GHz in our design and simulation. The SPICE model parameters were extracted using BSIMPro after 10, 20, 40, 60, and 100 min of DC stress, respectively. The MOSFET used in the Cadence

Conclusion

High tensile CESL700 and low strain SiN380 transistor performances subjected to HCI are examined experimentally. Both devices show consistent increase in threshold voltage and decrease in electron mobility as a function of stress time. The hot electron effect on the dual-band class-E power amplifier and LNA-mixer combination circuit RF performances have been examined in SpectreRF simulation using the extracted BSIM model parameters before and after hot electron stress. The output power of

Acknowledgement

The authors (W.-K. Yeh and C.-W. Hsu) wish to thank the United Microelectronics Company for providing test devices.

References (25)

  • J.-T. Park et al.

    RF performance degradation in nMOS transistors due to hot carrier effects

    IEEE Trans Electron Devices

    (2000)
  • J. Scholvin et al.

    RF power potential of 90 nm CMOS: device options, performance, and reliability

    Tech Dig Int Electron Devices Meet

    (2004)
  • Z. Chen et al.

    On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing

    IEEE Electron Device Lett

    (2000)
  • M.-C. Tang et al.

    Investigation and modeling of hot carrier effects on performance of 45- and 55-nm NMOSFETs with RF automatic measurement

    IEEE Trans Electron Devices

    (2008)
  • E. Li et al.

    Hot carrier induced degradation in deep submicron MOSFETs at 100 °C

    Tech Dig Int Reliab Phys Symp

    (2000)
  • C. Yu et al.

    MOS RF reliability subject to dynamic voltage stress – modeling and analysis

    IEEE Trans Electron Devices

    (2005)
  • C.-H. Liu et al.

    Degeneration of CMOS power cells after hot-carrier and load mismatch stresses

    IEEE Electron Device Lett

    (2008)
  • S. Naseh et al.

    Effects of hot-carrier stress on the performance of CMOS low-noise amplifiers

    IEEE Trans Device Mater Reliab

    (2005)
  • C. Yu et al.

    Channel hot electron degradation on 60 nm HfO2-gated nMOSFET DC and RF performances

    IEEE Trans Electron Devices

    (2006)
  • W.-C. Lin et al.

    Reliability evaluation of class-E and class-A power amplifiers with nanoscaled CMOS technology

    IEEE Trans Electron Devices

    (2005)
  • C. Yu et al.

    Electrical and temperature stress effects on class-AB power amplifier performances

    IEEE Trans Electron Devices

    (2007)
  • E. Xiao et al.

    Effects of hot carrier stress and oxide soft breakdown on VCO performance

    IEEE Trans Microwave Theory and Tech

    (2002)
  • Cited by (3)

    • Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

      2012, Microelectronics Reliability
      Citation Excerpt :

      This issue had been readily solved by using the multi-finger gate structure. However, some challenges still remain particularly on the hot-carrier reliability and accurate device models for circuit designs [7–9]. The DC and high-frequency models for the multi-finger nanometer MOS transistors are still not very precise because of some uncertainties on the charge and electric field distribution around the fingers [10].

    • Hybrid Beamforming System Diagnosis: Failure Modeling and Identification

      2021, IEEE Transactions on Wireless Communications
    • ANFIS-based computation to study the nanoscale circuit including the hot-carrier and quantum confinement effects

      2013, 2013 5th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2013
    View full text