Modeling the behavior of amorphous oxide thin film transistors before and after bias stress
Introduction
Amorphous oxide semiconductor Thin-Film Transistors AOS-TFTs have received much attention during the last years due to several interesting features, as for example high mobility, very high on/off ratio, low processing temperatures and possibility of fabrication on large areas. These characteristics are required for TFTs to be used in high frame rates active matrixes as AM-LCD and in AM-OLEDs [1]. Among AOS materials, amorphous In–Ga–Zn–O (a-GIZO) [1], [2], [3] and more recently Hf–In–Zn–O (HIZO) TFTs [4], which present some advantages with respect to GIZO TFTs, are been systematically studied. However, problems related to the stability with bias, temperature and illumination in these transistors, need to be understood and optimized, [5], [6], [7], [8], [9]. As can be seen from previous publications, devices can behave quite differently in dependence on fabrication processes and annealing, as well as on measurement conditions. In some cases, a parallel displacement of the transfer curves is observed, while in others, a hump or deformation on the curve appears. Another pendant task is the development of models suitable for designing with these transistors, which are frequently described using the same expressions as for MOS transistors. Recently a numerical model specifically developed for these devices was presented in [10]. In this case, authors showed that, if the active layers is sufficiently thick, part of it may not be completely depleted providing a back parallel current path that produces a deformation of the transfer curve as the device turns off. This effect, however, does not explain the deformation experimentally observed in the transfer curve of real devices, which appears only after DC or light stress.
In [11], it was demonstrated that the hump in the transfer characteristic observed in AOS TFTs devices after DC bias stress can be related to the effect of positive charges at the back interface of the bottom gate TFT structure. The presence of positive charges at this interface is expected to be more significant for passivated devices and will depend on processing conditions, device structure and materials used in the passivation layers, as well as on stressing conditions.
Since AOS TFTs are based on a TFT structure similar to a-Si:H TFTs and the active layer is also amorphous, is seems that their behavior should be closer to that of a-Si:H TFTs than to MOS TFTs. In this work we present a compact model and parameter extraction procedure based on the Universal Method and Extraction Procedure, UMEM, previously applied to other types of TFTs, in which specific characteristics of AOS TFTs are included. It is shown that it provides good agreement and can model the already mentioned hump.
Section snippets
Experimental part
A bottom gate AOS TFT, with channel width of 200 μm and channel length of 4 μm was simulated using SILVACO™ ATLAS, where the dielectric is a bilayer of 250 nm of SiNx and 50 nm of SiO2 with the SiNx contacting the gate electrode. The stack has an equivalent oxide thickness (EOT) Xeq of 189 nm. The active layer was 70 nm of AOS. The device is passivated with another SiO2/Si3N4 stack, 50 nm each. The gate, drain and source contact metal is Mo.
The effect of DC bias stress was simulated introducing the
TFT modeling
The typical behavior of carrier mobility in amorphous TFTs starts from a very low value well below VT, increases rapidly with VGS in the below threshold regimen and more slowly for VGS > VT. In above-threshold regime, the behavior of mobility in amorphous TFTs is well represented by [12]:where VT is the threshold voltage, γa is an extracted parameter defining the variation of mobility with gate bias and μFET1 is the field effect mobility for VGS – VT = 1 V, which can be
Analysis and discussion
To see the agreement between simulated and modeled curves, in Fig. 1, Fig. 2, Fig. 3, Fig. 4, modeled curves obtained using the indicated modeling and extraction procedure were also included. It can be seen than in all cases a good agreement is observed for both transfer and output characteristics, as well as for the transconductance. The hump in the linear transfer characteristic is well reproduced. Among specific features of the AOS TFTs behavior, it is seen that the behavior in above
Conclusions
We showed that the Universal Method and Extraction Procedure, UMEM, previously applied to other types of TFTs can also be applied for modeling the characteristics of amorphous oxide semiconductor TFTs. The procedure was complemented to represent specific characteristics of AOS devices as the hump observed in the transfer characteristics after DC stress. For validation, modeled curves were compared with simulated. The modeling procedure is useful for both circuit design applications and to study
Acknowledgements
This work was supported at CINVESTAV in Mexico by CONACYT Projects 56461 and 127978 and, at URV, by the Spanish Ministry of Science and Innovation (MICINN) under contract CSD2007-00007 (HOPE), by the Catalan Authority under project 2009SGR549; by PGIR/15 Grant and by ICREA Academia Prize.
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