Defect-centric perspective of time-dependent BTI variability

doi:10.1016/j.microrel.2012.06.120

Microelectronics Reliability

Volume 52, Issues 9–10, September–October 2012, Pages 1883-1890

https://doi.org/10.1016/j.microrel.2012.06.120 Get rights and content

Abstract

With the continuous downscaling of CMOS device dimensions, (i) The number of gate oxide defects in each device decreases to a numerable level, while their relative impact on the device characteristics increases. (ii) The properties of each defect, such as its capture and emission times and its impact, are voltage and/or temperature dependent and widely distributed. (iii) The occupation kinetics of each defect is known to be stochastic. All of these result in each of the nominally identical nm-scaled devices behaving very differently during operation, resulting in increasing time-dependent variability (heteroskedasticity). Consequently, the lifetime of nm-sized devices cannot be predicted individually, but can be described in terms of time- (or workload-) dependent distributions.

Introduction

As the vertical scaling of metal–oxide–semiconductor field effect transistor (MOSFET) devices continues, the oxide electric field increases and the so-called Bias Temperature Instability (BTI) becomes one of the most critical factors, complicating the qualification of the future technology nodes [1], [2], [3]. Furthermore, the number of stochastically behaving gate oxide defects in each device decreases to a numerable level due to the lateral downscaling, while their relative impact on the device characteristics increases. For all these reasons, BTI lifetime cannot be described any longer by a unique number, and BTI lifetime distribution has to be taken into consideration. As a consequence, even in the ideal case of the average BTI lifetime meeting the ITRS [4] specifications, a fraction of nanoscaled devices will fail at low overdrives. In this paper, the necessary physical understanding to predict the BTI lifetime distributions is developed and is introduced into an “atomistic” circuit simulator that takes realistic workloads into account.

We start by briefly reviewing the elementary definitions and experimental observations of BTI in large area and in nm-scaled devices. Contrary to the continuous relaxation curves observed on large area devices after bias temperature stress, giant discrete threshold voltage V_TH shifts are measured on nanoscaled devices and linked to drain random telegraphic noise (I_D-RTN) [5]. We then demonstrate that many properties of gate oxide defects, such as characteristic emission and capture times and V_TH impact can be directly extracted from BTI relaxation measurements in deeply scaled devices [6]. Afterward we show how the understanding of gate oxide defect properties can be used to explain time dependent BTI variability in deeply scaled technologies. Finally, an atomistic simulator based on existing industry-standard tools is presented for circuit assessments.

Section snippets

Bias Temperature Instability BTI in large and in nm-scaled devices

During CMOS circuit operation the devices typically undergo electrical stress at elevated temperature resulting in a shift of the device parameters such as its threshold voltage, channel mobility, transconductance, and subthreshold slope, instigating a decrease of the FET’s drive current. Since these instabilities are strongly accelerated by temperature T and gate bias V_G, they are known by the acronym BTI (Bias Temperature Instability). These phenomena are mainly the consequence of charging of

BTI: a non-steady state case of random telegraph noise

From the quantized recovery behavior observed in nanoscaled FETs it is straightforward to understand the recoverable component of BTI as the dynamic non-steady state case of random telegraph noise (RTN) [16]. As in the case of I_D-RTN, the large quantized ΔV_TH’s observed in Fig. 2 are explained by the non-uniform potential at the Si/SiO₂ interface caused by the random distributions of dopants in the channel and charged traps in the dielectric. The potential fluctuations produce variations of the

Kinetic of individual traps

As previously stated, a new methodology has been introduced to study the statistical properties of individual traps called time dependent defect spectroscopy (TDDS) [6]. In this section, we explain this methodology and the way to obtain the response of single gate oxide traps in a deeply-scaled FETs during DC and AC bias temperature stress. We demonstrate that the behavior of individual traps as a function of the stress time and duty factor is dictated by their characteristic capture and

Bias temperature variability

In large devices the random properties of many defects average out resulting in a well-defined lifetime as we showed in Section 2. However, in deeply scaled devices, the stochastic nature of a handful of defects becomes apparent. For this reason, the application of identical workload in such nanoscaled devices results in distributions of the parameter shifts [15], [29]. Therefore, the well-defined bias temperature instability (BTI) lifetime of large devices becomes widely distributed [12], [22]

Atomistic approach to BTI variability in circuit simulators

Our “atomistic” simulation framework proposed previously [22], [34] is shown in Fig. 15. It allows simulating the impact of workload-dependent variability on circuits (i.e., “reliability distributions under operating conditions”). The framework accepts the studied circuit in the form of a standard netlist. All or selected FET devices of the input circuit are annotated (i.e., “enhanced”) with unique defect properties randomly selected from distributions obtained previously on the simulated

Conclusions

In this article we have summarized some recent insights into BTI achieved from the comprehensive study of deeply scaled devices. Among the most relevant, it is the close link between RTN and the recoverable component of BTI, indicating that identically behaving traps are responsible of both effects. Useful information about the kinetic properties of individual traps has been straightforwardly extracted from the recently developed technique TDDS. This helped to understand the charge exchange

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View full text

Defect-centric perspective of time-dependent BTI variability

Abstract

Introduction

Section snippets

Bias Temperature Instability BTI in large and in nm-scaled devices

BTI: a non-steady state case of random telegraph noise

Kinetic of individual traps

Bias temperature variability

Atomistic approach to BTI variability in circuit simulators

Conclusions

Microelectron Reliab

Microelectron Eng

Statistics of multiple trapped charges in the gate oxide of deeply scaled MOSFET devices—application to NBTI

IEEE Electron Device Lett

RTS amplitudes in decananometer mosfets: 3-D simulation study

IEEE Trans Electron Dev

Simulation of statistical aspects of charge trapping and related degradation in bulk mosfets in the presence of random discrete dopants

IEEE Trans Electron Dev

Comprehensive analysis of random telegraph noise instability and its scaling in deca–nanometer flash memories

IEEE Trans Electron Dev