An on-chip sensor to measure and compensate static NBTI-induced degradation in analog circuits

Abstract

Negative Bias Temperature Instability (NBTI) degrades the life-time of both the analog and digital circuits significantly and has become a major concern in nanoscale regime. In analog circuits, the DC biasing voltage is always present irrespective of the input signal. Therefore, coupled with high operating temperature (due to dynamic switching and high packaging density of SoC) and constant DC bias, there would be continuous NBTI stress in analog circuits with minor or almost no recovery. Moreover, mismatch and input referred offset voltage caused by NBTI in differential pairs, current sources and cascode stages can cause instantaneous, intermittent or catastrophic failure after certain time period. The problem of NBTI is usually addressed by leaving large design margins and/or employing adaptive body bias and dynamic voltage scaling calibration techniques using on-chip sensors or monitors. We propose an ultra low power and low area on-chip NBTI sensor which can be used to accurately sense the NBTI degradation in analog circuits. We have shown that the temporal degradation of PMOS transistor in analog circuits has high correlation to the output variation in proposed NBTI sensor. We also propose a simple circuit for generating accurate body bias to compensate temporal NBTI. We have demonstrated how using the proposed sensor and the adaptive body bias mechanism can be used to compensate NBTI degradation in various analog circuits. Measurement results are also provided for the proposed sensor fabricated in commercially available 65 nm process.

Introduction

As CMOS process technology scales beyond 100 nm to provide denser and faster integration, the aging as well as variability issues are limiting their performance and lifetime [1]. Many reliability issues have become significant as oxide thickness is scaled towards 1 nm and voltage margin is reduced. In particular, Negative Bias Temperature Instability (NBTI) is the leading reliability concern for nano-scale transistors. NBTI is a result of continuous trap generation in Si–SiO₂ interface of PMOS transistors. In bulk-MOSFETs, structural mismatch at the interface creates dangling bonds which acts as charged interfacial traps. To prevent this structural mismatch, hydrogen passivation is applied at the silicon surface after the oxidation to convert the dangling Si atoms to Si–H atoms. However, with the age, voltage stress and interaction of holes with passivated Si atoms, these Si–H bonds break and again form the interfacial traps and neutral H atoms. These interfacial traps leads to an increase in the threshold voltage (V_TH) of PMOS devices [2]. The neutral H atoms can either form H₂ molecules or can anneal the existing traps.

NBTI is typically seen as a threshold voltage shift after a negative bias is applied to a MOS gate at elevated temperature, mainly affecting the PMOS transistors. Due to high electric field in the channel, NBTI leads to increase in V_TH, decrease in drain current (I_DS) and mobility (μ) and is a function of time and stress condition [3]. Such degradations are likely to cause short term failure of transistors and impact the product yield during burn-in tests. The use of nitrided oxides for controlling the gate leakage current in transistors has shown to exacerbate the NBTI induced degradation process [4]. According to International Technology Roadmap for Semiconductors (ITRSs) [5], NBTI induced degradation is one of the most prominent challenges for future process development and reliable circuit design.

The impact of NBTI on digital circuits has been studied extensively as they are subject to gate-source voltages which are comparable to supply voltages. Several techniques have been proposed in recent years for mitigating the effect of NBTI degradation mostly for digital circuits. Most of them are either post-silicon repair techniques, such as analog voting [23], or based on sensing the performance degradation using on-chip NBTI sensors in bulk. Shown in [6], the sensing circuitry first senses the degradation, which is then used to adaptively size the keeper transistor to achieve the required robustness. The drawback of this technique is extra overhead in terms of area and power for sensor and calibration circuits. SRAM array leakage was used in [1] as a measure of Process, Voltage and Temperature (PVT) variation and Adaptive Body Bias (ABB) was applied as repairing mechanism. This leakage based sensing method suffers from temperature variations, which results in inferior correction. The approach proposed in [7], [8] employs Phase Locked Loop (PLL) and Delay Locked Loop (DLL) based techniques to sense the degradation due to NBTI, CHC, etc. These approaches are not very accurate and incurs huge area and power penalty for sensing and compensation.

Many sensors are also reported in the literature [1], [6], [7], [8] which can monitor process variation, Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB) degradation. However, these sensors cannot be used for correcting or calibrating static NBTI in analog circuits because these sensors have digital characteristics and themselves undergo recovery when the gate stress is removed (i.e. V_GS = 0). Accurate calibration or compensation in analog circuits requires sensors that degrades at the same rate as the circuit itself.

NBTI is reported to be a major reliability concern in analog circuits and is shown by device level characterization for performance metrics [9]. In analog circuits usually a percentage change in I_DSAT is defined as parametric failure for analog operations [10]. Analog circuits are not subject to high drain and gate bias but tighter tolerance, continuous DC stress and stringent matching requirements can limit the reliability of analog circuits due to NBTI mechanism. Mismatches among the current sources, differential pair, etc. induced by NBTI can cause performance degradation, instantaneous or catastrophic failure after certain time. In our earlier work [11], we showed selective overdesign based technique using commercially available 130 nm process to improve the performance of analog circuits in presence of temporal degradations. Our approach also resulted in area and power overhead for tolerating the static NBTI degradation.

This paper is based on our previous study [12]. In this paper, we present a low power and low area on-chip NBTI monitor/sensor specifically for analog applications. This sensor directly translates the temporal degradation in V_TH of PMOS transistors (caused by NBTI) into shift in reference voltage (V_ref). The change in the sensor output has direct correlation with temporal NBTI degradation and minimal correlation with parameters such as supply and process variations. The paper is organized as follows. In Section 2, we briefly explain Reaction–Diffusion (RD) NBTI model and illustrate examples showing the effect of NBTI on analog circuits designed in commercially available 65 nm CMOS process. In Section 3, we explain the detailed architecture and working mechanism of our proposed NBTI sensor. Section 4 proposes a method to generate body bias for compensating static NBTI. Simulation setup and measurement results for NBTI sensor are presented in Section 5. Section 6 presents the application examples and finally, Section 7 summarizes the findings and contributions of this work.