PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
Introduction
In advanced nanoscale CMOS process, electrostatic discharge (ESD) protection has become the major concern of reliability for integrated circuits (ICs). The nanoscale device with thinner gate oxide and shallower diffusion junction depth seriously degrades the ESD robustness of ICs and raises the difficulty of ESD protection design for ICs implemented in nanoscale CMOS technology [1]. Therefore, an efficient ESD protection element is highly required by IC industry. To achieve whole-chip ESD protection, the power-rail ESD clamp circuit is a vital basis, as shown in Fig. 1 [2]. In Fig. 1, the power-rail ESD clamp circuit can protect the internal circuits with efficient discharging path under various ESD stress conditions.
The ESD clamp device drawn in the layout style of big field-effect transistor (BigFET) had revealed excellent ESD protection performance in advanced nanoscale CMOS ICs [3], [4], [5], [6]. For the ESD-transient detection circuit, there are two design skills, the RC-delay [3], [4] and the capacitance-coupling designs [5], [6], to effectively trigger the BigFET transistor under ESD stress condition. The traditional RC-based power-rail ESD clamp circuit is shown in Fig. 2. The RC time constant is generally designed large enough about several hundreds nanosecond to keep the ESD clamp device at “ON” state under ESD stress condition. However, the extended RC time constant of the ESD-transient detection circuit suffers not only the larger layout area but also the mis-trigger of the ESD clamp circuit under fast-power-on or “hot-plug” applications [3].
Besides, low standby leakage of the ESD clamp circuit is highly demanded by the hand-held, portable, and battery powered products. In advanced CMOS technology, the leakage current of NMOS was often larger than that of PMOS in the same device dimension. Therefore, PMOS is suggested to be used as ESD clamp device [7].
In this work, the parasitic capacitance of the ESD clamp PMOS transistor drawn in BigFET layout style is used as a part of ESD-transient detection circuit. This new design has been verified in a 65 nm 1.2 V CMOS technology. From the measured results, the proposed power-rail ESD clamp circuit has features of area efficiency, low leakage current, and high immunity against mis-trigger.
Section snippets
New ESD-transient detection circuit
The new proposed power-rail ESD clamp circuit is illustrated in Fig. 3. The ESD-transient detection circuit consists of two transistors (Mn and Mp), two resistors (Rn and Rp), and diode string. The PMOS transistor drawn in BigFET layout style (Mclamp) is used as ESD clamp device. The gate terminal of Mclamp is linked to the output of the ESD-transient detection circuit, which can command Mclamp at “ON” or “OFF” state.
In Fig. 3, the diode string in ESD-transient detection circuit is used to
Experimental results
The test chip to verify the proposed power-rail ESD clamp circuit has been fabricated in a 65 nm 1.2 V CMOS process. As shown in Fig. 6a and b, the layout area of the proposed ESD-transient detection circuit is reduced by 54.5% from that of traditional RC-based one.
Conclusion
New power-rail ESD clamp circuit with adjustable holding voltage has been successfully verified in a 65 nm 1.2 V CMOS technology. The proposed ESD-transient detection circuit adopts the capacitance-coupling mechanism to command the ESD clamp PMOS transistor. From the measured results, the proposed design has excellent immunity against mis-trigger and latch-on under the fast power-on condition. The proposed ESD-transient detection circuit is also efficient in layout area and standby leakage, which
Acknowledgments
The authors would like to thank Mr. Yung-Chih Liang of Industrial Technology Research Institute (ITRI) for his valuable technical discussion. The authors would also like to express their thanks for the TLP equipment from Hanwa Electronic Ind. Co., Ltd., Japan. Especially, thanks to Mr. Takumi Hasebe, Mr. Keiichi Hasegawa, and Mr. Masanori Sawada for setting up the TLP measurement system at National Chiao-Tung University, Taiwan.
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