Experimental study of bump void formation according to process conditions
Highlights
► Void formation reduced with decreasing SRO. ► Void area ratio reduced with decreasing SRO. ► Voids were formed in the form of double-walled and ball shape. ► Void generation by the entrapment of flux in the molten solder.
Introduction
Solder bump has been widely used in connections between substrate and chips in electronic packaging. Voids, which are bump defects, have become a critical issue as they affect the reliability of solder joints since a fine pattern is required due to the small form factor of electronic devices. It has been generally reported that voids in solder bumps are formed by the entrapment of volatiles during the reflow process, the trapping of air during the screen printing and reflow process, by particles such as dust and desmear residues on the substrate, or a combination of these. These voids reduce the cross-sectional area of the solder joints and can have a negative impact on product performance, both mechanically and electrically [1]. Process variables that affect the formation of voids are well known, and include reflow temperature profile and atmosphere, the properties of the materials comprising the solder paste, the geometry of the pattern, and the thickness of the screen printing mask. Numerical studies [2], [3], [4], studies on heat flux direction [5], [6], [7] and studies on reflow profile and other factors [8], [9] affecting the formation of voids have been reported. In this study, two kinds of Sn–Ag–Cu solder paste, two kinds of pad finishes, two screen printing mask opening (MO) sizes, and three solder resist opening (SRO) sizes were used to compare void formation. In order to minimize the impact of heat flux, a thin substrate was prepared. A solder paste that consisted of very small particles with an average size of about 6 μm for fine pitch bumping was used to observe voids formed in a fine bump. In an attempt to elucidate the cause of the voids, an additional analysis of bump cross-sections was performed with a focused ion beam, since X-ray can only observe the presence of voids and measure void size. Finally, to observe flux motion, real-time observation during a reflow process was conducted by a thermal video system.
Section snippets
Experimental
The substrates used in this study are shown in Fig. 1. Fifty-micrometer-thick Ni metal masks with 70 and 80 μm opening size were prepared for screen printing. Lead-free solder paste-A and paste-B (Sn–3.0Ag–0.5Cu) were used for printing. Screen printing was carried out using a squeeze pressure of 0.3 MPa and a speed of 50 mm/s. The printed solder was reflowed in a table-top reflow oven (RDT-250C, Malcom Co., Ltd.). A detailed reflow profile is shown in Fig. 2. It was difficult to apply a typical
Void indices
Fig. 5 shows X-ray images of voids in paste-A using a MO size of 70 μm as the SRO size on the electroless nickel electroless palladium immersion gold (ENEPIG) and organic solderability preservative (OSP) pad finish substrate. Arrows indicates voids in the bump. In the case of MO size of 80 μm condition and paste-B, as shown in Fig. 5, X-ray inspection was performed and the void size was measured.
In order to determine the locations of voids, cross-sectional observations were made using an optical
Conclusions
This paper focused on the influence of process parameters on void formation and sought to verify the underlying mechanism. The main variable that affected void formation was the type of pad finish and the SRO size. Depending on the kind of pad finish, the solder paste also gave some influence on void formation. Screen printing mask opening size had little effect on void formation. Voids occurred less in the ENEPIG pad finish than the OSP pad finish with both kinds of solder paste. Void radius,
Acknowledgements
This study was supported by a grant from the Advanced Materials and Process Research Center for IT (AMPIT) and Samsung Electro-Mechanics Company Advanced PCB Research Center (SARC) at Sungkyunkwan University in South Korea.
References (9)
- et al.
Solder joint reliablity of BGA, CSP, Flip chip, and fine pitch SMT assemblies
(1997) - Goenka L, Achari A. Void formation in flip chip solder bumps – Part 2. In: Proceeding of the 19th IEEE/CPMT, symposium;...
- et al.
Simulation of void growth in molten solder bumps
J Electron Packag
(2003) - et al.
A numerical study of void nucleation and growth in a flip chip assembly process
Modell Simul Mater Sci Eng
(2010)
Cited by (2)
Heat and fluid flow in high-power LED packaging and applications
2016, Progress in Energy and Combustion ScienceCitation Excerpt :However, the continuing increase in packaging density of LEDs has resulted in a major challenge concerning on reliability of this interconnect material. For the solder joints, one primary factor that hinders joint reliability is the void formation during the reflow process [119–126]. Panton et al. [119] simulated void growth in molten solder bumps.
Fabrication of 30 µm Sn Microbumps by Electroplating and Investigation of IMC Characteristics on Shear Strength
2023, Electronics (Switzerland)