A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs

Abstract

As CMOS feature sizes decrease into nanometers, manufacturing defects are becoming a growing concern in electronics industry. SRAM-based FPGAs, which have been widely used in many applications, are also affected by technology downscaling. Since the cornerstone of their logic and interconnect resources is the multiplexer, this work introduces a defect-tolerant multiplexer, more resilient to single transistor defects (stuck-open, stuck-closed and gate shorts) than other multiplexer architectures studied in the paper, and more area-efficient than other existent hardening techniques.

Introduction

As process technology scales to nanometers, the amount of defects in electronic circuits is expected to increase, becoming a major issue in current and future technologies. This is especially due to manufacturing-induced problems leading to a decrease in the yield [1], [2]. Indeed, the yield has become a fundamental criterion in defining an implementation’s cost, as important as area, speed and power consumption which intervene in the tradeoff that a designer has to make [3].

Thanks to their reconfigurability, low development costs and reduced time-to-market, SRAM-based FPGAs are widely used in several applications from networking to space applications [4], [5], [6]. Therefore, from the manufacturer viewpoint, incorporating defect tolerance is crucial to enhance the yield and relaxes the stringent constraints of the manufacturing process [7], [8], [9]. Many techniques have been proposed in the technical literature for repairing FPGAs when they are affected by permanent faults [10], [11], [12].

As a matter of fact, most of the current defect tolerance (hardening) schemes introduce redundancy in the architecture to combat defects. Several hardening techniques at different granularity levels have been proposed to better the FPGA’s robustness to defects [13], [14], [15]. Nevertheless, these techniques assume spare resources and/or consume too much area to be cost-effective.

This work aims at improving the robustness of the FPGA’s basic blocks (logic and interconnect), which are mainly composed of 2:1 multiplexers (Mux2s), by proposing a Mux2 design tolerant to single transistor defects of the types: stuck-open, stuck-closed and gate shorts. We used the STM 65 nm technology to create this Mux2, called Z-Mux, from Tristate cells of the CORE65LPSVT standard cell library. We compared the Z-Mux with the common Mux2 implemented with CMOS transmission gates, and with other Mux2 architectures. The proposed Z-Mux proved to be the most robust of all with respect to the aforementioned defects. Besides, it consumes less area than other hardening methods like the Triple Modular Redundancy (TMR) technique [16], [17], [18], the quadrupled transistor technique [19] and the Multiple Short-Open (MSO) technique [20]. In fact, the TMR being one of the most popular fault tolerance approaches, tolerates one defective module, assuming a perfect working voter. The proposed Z-Mux proved to be even more robust to transistor defects than the TMR technique applied on the common Mux2, using a simple fault-tolerant voter introduced in [21]. It was demonstrated that this voter is tolerant to single faults.

The remainder of this paper is organized as follows: Section 2 introduces the Z-Mux and the other studied Mux2 architectures. In Section 3, the defect tolerance analysis is explained. Then, simulation results are discussed in Section 4 and the Mux2 architectures are compared in terms of reliability and size. Finally, concluding remarks are drawn in Section 5.