A novel partial-SOI LDMOSFET (>800 V) with n-type floating buried layer in substrate

Highlights

• New P-SOI LDMOS structure with n-type floating buried layer in the substrate.

• The proposed structure improves the BV and reduces specific on-resistance.

• Self-heating effects are also suppressed in the proposed structure.

Abstract

In this paper, a novel high voltage lateral double diffused metal–oxide–semiconductor (LDMOS) field effect transistor based on partial silicon-on-insulator (PSOI) technology is proposed and investigated based on the numerical simulations. The structure is characterized by an n-type floating buried layer (NFBL) in the substrate under the silicon window near the drain. The buried layer in the substrate modulates the lateral and vertical electric field, which results in the electric field of the drift region distributed uniformly. Therefore, the breakdown voltage (BV) of the device is significantly improved. The influences of the key parameters on device performance of the proposed structure are discussed. Moreover, the self-heating effect (SHE) is greatly alleviated duo to the silicon window helps thermal conduction to the substrate, which improved the reliability of device application.

Introduction

Silicon-on-insulator (SOI) technology provides clear advantages over commonly used junction isolation (JI) technology such as low leakage current, low parasitic capacitances, high integrated density, higher switching speed and ideal isolation between devices [1]. SOI-based lateral double diffused MOSFET (LDMOS) has been widely used in smart power integration circuit (SPIC), such as power conversion, automotive, consumer and medical, which contributes to its near ideal compatibility with advanced VLSI technologies. Various structures have been proposed to improve the performance of the LDMOSFET on SOI substrate [2], [3], [4], [5], [6], [7], [8].

However, due to exist of buried oxide layer (BOX), two main problems limit the application of SOI LDMOS in power and high-voltage ICs. These are the SHE and low vertical BV. SHE is caused by the poor thermal conduction of BOX, which will induce various reliability problems. Furthermore, the vertical BV are expressed as V_bv = 0.5t_sE_s + E_It_i for the conventional SOI LDMOSFET, where E_s and E_I are the electric field of the silicon layer and BOX, t_s and t_i are the thickness of the silicon and BOX, respectively. It is difficult to achieve BV exceeding 600 V for conventional SOI power devices with uniform doping concentration because of the thickness limitation of the SOI layer and BOX layer. Partial-SOI technology [8], [9], [10], [11], [12], [13], [14], [15], [16] is an ideal solution to suppress two problems mentioned above. A silicon window helps thermal conduction to the substrate, which can alleviate SHE significantly [17]. Furthermore, the sharing of potential across the BOX and substrate results in higher BV for similar SOI thickness in comparison to conventional SOI devices where most of the applied voltage is supported by the BOX.

In this paper, a new partial-SOI LDMOSFET (PSOI) with n-type floating buried layer in substrate (NFBL-PSOI) was proposed, which introduces an n-type floating layer in partial-SOI substrate to modulate the lateral and vertical electric field in the drift region. A BV of 823 V is obtained for the proposed structure compared with 456 V and 240 V for the conventional partial SOI LDMOS (con-PSOI) and conventional SOI LDMOS (con-SOI) structure. Moreover, the SHE is also greatly reduced in the proposed structure compared with con-SOI. The influences of the key parameters on device performance of the proposed structure were discussed by 2-D Sentaurus TCAD device simulator.