Influence of solder bump arrangements on molded IC encapsulation

Highlights

• The scaled-up IC encapsulation was carried out to validate the numerical studies.

• A total of five models with solder bump arrangements were studied numerically.

• The downward chip deformation resists the EMC flow during the filling process.

• Solder bump arrangement crucially influences the deformation and stress of IC chip.

Abstract

This paper presents a fluid–structure interaction (FSI) analysis of ball grid array (BGA) package encapsulation. Real-time and simultaneous FSI analysis is conducted by using finite volume code (FLUENT) and finite element code (ABAQUS), which are coupled with MpCCI. A BGA integrated circuit (IC) package with different solder bump arrangements is considered in this study. In the FSI analysis, effects of solder bump arrangements on pressure distribution, void, deformation, and stress imposed on the IC structures are investigated. The maximum deformation and maximum stress on the silicon chip and solder bumps are evaluated. The findings indicate that the full-array solder bump package encounters lower stress and deformation during encapsulation. The void formation of each solder bump arrangement is examined. Scaled-up encapsulation is performed and the predicted flow front advancements are substantiated by experimental results. Results demonstrate the excellent capability of the proposed modeling tools for predictive trends of IC encapsulation. Thus, better understanding of IC encapsulation is provided to engineers and package designers in the microelectronics industry.

Introduction

IC packaging production tends toward high performance, reliability, miniature size, and low cost. In the microelectronics industry, ball grid array (BGA) technology has enabled the design of IC packages with high density of interconnection in a miniature size. BGA types such as the plastic ball grid array [1], multi-chip ball grid array [2], ceramic ball grid array [3], and flip-chip ball grid array [4] have been used in various types of IC packages in diverse applications. In IC encapsulation, the encapsulant is fed into the mold cavity to encapsulate the silicon chip to enhance package reliability. The encapsulant protects the IC structures (e.g., silicon chip, solder bump, IC paddle, and wire bond) from hazardous environmental factors such as high temperature, vibration, and moisture. The interaction between encapsulant and IC structures during the encapsulation may induce unintended deformation, stress concentration on the chip, and solder bumps. Extreme deformation and stress imposed on IC structures may result in initial package defects during the subsequent process.

In the IC encapsulation, transfer-molding technology has been established as a method of transferring the encapsulant into the mold cavity. Costlier and non-transparent molding tools have restricted the visualization of the encapsulation process. Thus, simulation modeling provides insights into fluid–structure interaction (FSI) phenomenon in the encapsulation process. Rapid development of commercial software such as PLICE-CAD [5], FORTRAN [6], FLUENT [7], C-MOLD [8], [9], and Moldex3D [10] has facilitated the prediction of various IC packages. However, this software can only handle the fluid flow analysis. Likewise, computer-aided engineering (CAE) software assists in the prediction of wire sweep [11] and paddle shift [12] in the encapsulation process. To perform the real-time FSI analysis, additional software is required to transfer the analysis data from each solver simultaneously. Otherwise, FSI analysis can be performed by using the de-coupling method, which solves both fluid and structural analyses separately. The better understanding of IC encapsulation and enhancement of IC packages can be achieved through the virtual modeling technique.

To increase package reliability, void formation, interface delamination of the silicon chip and epoxy-molding compound (EMC) material, and shrinkage of EMC and deformation of chip and solder bumps that occur in IC encapsulation should be minimized. Improper selection of EMC and processing parameters [13] for IC encapsulation is the key factor in void formation. Therefore, the optimization of processing parameters [14] and mold design (position of gate and vents and gate and vent size) is essential to the encapsulation process. The EMC properties such as the elastic modulus, coefficient of thermal expansion (CTE), chemical cure shrinkage, and physical characteristics of IC packages should also be optimized to reduce interface delamination [15]. Typically, material properties [16], processing temperature, void in encapsulant, and solder joints [17] may contribute to the production of solder joint cracks. The stresses exerted and deformation created on the silicon chip and solder joints during the encapsulation process may cause initial defects and lead to the malfunctioning of the IC package.

In the conventional underfill process, the encapsulant is dispensed to fill the intermediate space between flip chip and substrate, which consists of solder bumps. During the filling process, the encapsulant is driven by the capillary effect of the intermediate space. The understanding of underfill flow behavior can be achieved through the numerical modeling. Wan et al. [18] reviewed the recent advances modeling of the underfill process in the flip chip packaging. They highlighted a few research gaps in the underfill process, including (i) the solder bump’s pattern and its functionality, (ii) effective model of underfill flow for various solder bumps’ pattern and (iii) modeling of void formation. These indicated that the significance of solder bump’s pattern to the fluid flow behavior during the process.

High productivity and low cost in the manufacturing process are the desired goals of engineers in the microelectronic industry. Conventional flip chip packaging requires more filling time, which affects the subsequent production speed of IC packages [19]. Alternatively, the implementation of transfer molding technique [20] can reduce the number of processing steps, where the underfill and encapsulation are performed in a single molding step. Thus, this process enhances the overall productivity by reducing the production time, improving package reliability, enhancing package co-planarity, and reducing the stress concentration on the solder bumps [21]. Moreover, this molding technique also helps in reducing thermal mismatch [22], providing better electrical [23], enhancing stress performance [24] and thermal performance [25]. In addition, the application of molded underfill (MUF) technique in the flip chip ball grid array packaging process yields shorter processing time and enhanced the package reliability by using MUF material [24].

The fluid–structure interaction (FSI) phenomenon that occurs between encapsulant and silicon chip during encapsulation is complicated. Visualization of the actual encapsulation process is difficult and costly. Based on our previous studies [26], [27], the FSI investigation of the BGA IC package was extended by considering the effects of solder bump arrangements. FV-based (FLUENT 6.3.26) and FE-based (ABAQUS 6.9) software were connected by the MpCCI software to perform real-time FSI analysis. The Non-Newtonian power law model and volume of fluid (VOF) model were employed to model the encapsulant behavior and flow front tracking. Real-time and two-way interaction analyses were implemented. The fluid data that interacted with the structure were sent to ABAQUS through MpCCI and vice versa. Scaled-up IC encapsulation was conducted to confirm the capability of the proposed modeling tools. The flow front advancement was substantiated by experimental results.