Numerical analysis of thermo-mechanical and mobility effects for 28 nm node and beyond: Comparison and design consequences over bumping technologies
Introduction
Following the race for miniaturization and increased performances, semiconductor industry continuously needs to integrate novel concepts [1]. The whole manufacturing stages, from the Front End of Line (FEoL) to the Back End of Line (BEoL) are day by day improved; this paper proposes to focus on assembly processes: the latter of these consist in bridging the scales from the die to the package and in guarantying the electrical connection within the device. To do so, the Flip-Chip (FC) scheme has beneficially complemented the historical ultrasonic wire bonding method, at least for high performance applications [2], [3], [4], [5]. The connecting functions of FC processes are assumed by the bumps, which can involve several kinds of materials: for examples ranked from older to newer date of introduction, the used materials for the core part of the bump are eutectic, lead free, and nowadays copper becomes widely adopted. Furthermore, in combination with the “Moore Law” depicting transistors and packages downscaling, the so-called “More than Moore” concept, consisting in the development of specific integration stages at the chip level is one of the most attractive solutions: three-dimensional integrated circuits (3DICs) have hence been introduced to push the inherent limits of two-dimensional products. Those novel integration flows help to achieve industry constrains, for both performances and economic concerns such as time to market, yield and cost.
However, huge technological challenges must be faced to ensure product integration and lifetime [6], [7]. Amongst those, the thermo-mechanical issues, due to high temperature processes and distinct coefficient of thermal expansions (CTE) of materials are promoted. Indeed, lower dimensions, finer pitches and the use of low-k dielectrics in BEoL interconnects are some of the detrimental factors leading to Chip-Package Interactions (CPIs). CPIs are two folds: on one hand strained materials and interfaces can fail due to overstress; on the other hand, strained silicon channel modifies Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) behavior [8], [9].
This paper proposes to carry out over recent bumping process generations, a numerical analysis of the electrical mobility variation induced by the thermo-mechanical stress: Flip chip solder bumping with mass reflow at first, then the copper pillar bumping using capillary under filling scheme, and finally the micro-copper pillar (μCP) bumping with Wafer Level Underfill (WLUF) material.
Thanks to a comprehensive analysis, FEoL designers will be able to consider BEoL and packaging constraints during conception phases. Indeed, designers cannot ignore assembly components at the early stage of the product definition anymore. More precisely, FEoL design rules must be compliant with BEoL ones, and a co-design flow should be employed. Furthermore, depending on the company and the technologies, divergent exclusion rules for the transistor placement are adopted to prevent any performance drop such as variability and frequency drift. However, in addition to the performance questions, excluding some MOSFETs in a certain region at the bump neighborhood is obviously a detrimental factor for products, since the impacts on die size and, by consequence, on cost are straightforward [10], [11].
Beyond the stress analysis and thanks to an evaluation of the strain induced electrical changes, this paper provides design recommendations for MOSFETs placement on the silicon die with respect to the bump region. Numerical simulations are hence employed to assess thermo-mechanical effects of bumping processes on mobility, and to draw placement and exclusion rules.
Finally, the core chapters of this paper are complemented with appendices exploring both material laws and geometrical effects of the bump in one of the solder configuration. This aims to precise the scope of applicability of the results, to validate the modeling approach and to provide additional clues for process optimization.
Section snippets
Simulation strategy
To address numerically the effects of bumping process on device performance and thus to help CMOS28 nm products integration, typical test cases are chosen accordingly. More precisely, a finite element modeling (FEM) methodology, complemented by a specific post processing computation is set: this covers the evaluations of the thermo-mechanical stress at the bump vicinity, the transmission mechanisms to the silicon device region and, based on the linear piezo resistive theory, the stress effect on
Geometries and material properties
For comparison purpose, a similar approach is adopted for whole models: due to symmetries, a quarter of the structure is simulated and three-dimensional (3D) models are built. Boundary conditions are set to mimic isolated bump, and results for finer pitch can be extrapolated thanks to the superposition principle.
Typical cases are chosen for this study: materials, stacks and geometries for the die features reproduce an existing CMOS28 nm product, and the parameters are set as follows:
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Bump shapes:
Results
In this section, modeling results at various scales are presented. For the SnAg configuration (FC), the results has been detailed in [22] and analysis is here particularly focused on the CP and the μCP ones. However, a comparative study including the whole three assembly technologies will be discussed.
The induced stresses inside the copper pillar are firstly presented to depict residual strain states. Then, relaxation mechanisms in the silicon region are investigated. Fig. 5, Fig. 6 show the
Conclusion
This paper explores stress induced mobility changes over three major bumping processes. A numerical comparative analysis over advanced assembly generations is carried out. To do so, finite element models are built for SnAg flip chip, copper pillar flip chip and μ copper pillar bumping. This work aims to draw design recommendations for MOSFET placement and to provide specifications to be included in conception tools. This allows to ensure adherence to product specifications while technologies
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