Stress analyses of high spatial resolution on TSV and BEoL structures
Introduction
Advanced microprocessors utilizing low-K and ULK materials have led to new reliability concerns due to the tremendously changed material and interface properties in the BEoL stack. Chip Package Interaction (CPI) became an important issue for interfacial crack initiation and propagation in the stack. Ongoing 3D-IC-integration development introduced new critical problems corresponding to the used TSV technology. Because of the high CTE (Coefficient of Thermal Expansion) mismatch between the TSV metals and the surrounding silicon, significant stresses occur nearby TSVs. As a result, charge carrier mobility as well as mechanical device reliability is affected. So, reliable knowledge and control of local critical stress states is an important precondition of successful device design.
Numerical simulation and failure modelling on complex 3D-integrated packages still is a challenge. Although whole manufacturing process simulations are carried out, they can suffer from multisided necessary simplifications. Right identification of material laws and respective property determination is another difficulty. Hence, Finite Element Analysis (FEA) of sub-components and sub-process steps is a common approach. Already frozen intrinsic stresses for a particular starting point of an FEA is one of the essential input entries needed. Fig. 1 illustrates this fact for a case study of the authors on interface reliability in a BEoL stack. Although a trend estimation of crack propagation risk comparing different dielectrics materials/crack propagation paths is possible, no real failure risk can be estimated, because of missing reliable absolute values of the Energy Release Rates (ERR), as seen from Fig. 1.
Incorporating stress measurement methods to feed simulations with right initial stresses can be an appropriate solution. Basic requirements on such tools would be
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sufficient spatial stress resolution laterally and into depth (some μm to a few 10 nm),
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no or low degree of destructive measurement,
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measurement feasibility on components and systems as manufactured,
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at least low field measurement.
Among the high spatial resolution methods demonstrated on BEoL stacks, TSVs or similar small objects, we find X-ray and electron diffraction [1], [2], stress relief techniques [3], [4] and microRaman spectroscopy [5]. Diffraction based methods require sufficiently crystalline materials. Higher lateral spatial resolution is limited to electron diffraction (some 10 nm) or synchrotron sources with small spot sizes (some 100 nm). Electron diffraction allows relative measurements in single crystals only. Diffraction measurements on synchrotrons are expensive with limited availability.
At first glance microRaman is an attractive method with feasible and fast stress mapping, however restricted to Raman-active materials, like semiconductors. In the past many groups applied this method to access stresses around TSVs [5], [6]. However, at second glance stress extraction from Raman shifts is not as simple.
Section snippets
Applied stress measurement approaches
Two experimental stress measurement methods are reported in this work – a stress relief technique carried out in Focus Ion Beam equipment (FIB), and microRaman spectroscopy. Both of methods possess high lateral spatial resolution, even though the first one outmatches by an order of magnitude. Furthermore, they differ in their sensitivity and response to the particular stress tensor components relevant for the residual stress state nearby TSV structures or in BEoL stacks. I.e. they are
fibDAC stress relief measurements
Stress relief measurements have been performed in a ZEISS Auriga60 FIB using magnification typically between 10,000 and 100,000. In order to reduce processing time due to stage tilts and re-adjustments, ion milling was carried under 54° observing the object with the SEM under 0°. Low current deposition mode has been used for ion milling.
Fig. 3 shows a first example of stress measurement carried out on a TSV at room temperature, Cu filled and with 8 μm diameter. Obtained experimental stress data
Finite Element Analysis (FEA)
In order to avoid thermo-mechanical failures or charge carrier mobility changes around TSVs, extended FEA is being performed to simulate and understand the impact of TSVs. Fig. 10 shows a typical failure analysis performed by FEA for a TSV application. Accumulated plastic strain in Cu due to thermal cycling leads to Cu pumping and influences the failure behaviour. Bi-material fracture mechanics analyses e.g. by modified Virtual Crack Closure Technique (VCCT) are a common approach to evaluate
Conclusions
It has been shown how a combination of local stress measurement techniques, as microRaman and fibDAC stress relief, and Finite Element Analysis (FEA) can be combined to evaluate stresses caused by TSVs and BEoL stacks. Experimental results can be utilized to validate FE modelling and to make sure that simulations lead to trustworthy data. Moreover experimentally found intrinsic stresses can be used as input data for FEA modeling, if not the whole component manufacturing process is emulated by
Acknowledgements
Some of the referred to Raman measurements have been performed at Fraunhofer IZM. We acknowledge the assistance by A. Gollhardt. We also acknowledge some simulation work carried out by U. Hoelck, at that time being with Technical University Chemnitz. Part of the work reported has been funded by the BMBF Germany (Cluster of Excellence “MERGE”).
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