Physically-based extraction methodology for accurate MOSFET degradation assessment
Introduction
The precise extraction of MOSFET parameters is a major concern for both characterization and circuit design purposes in microelectronics. With the continuous device down-scaling an accurate extraction of the physical parameters recorded as a function of the stress is fundamental to get the device behavior for any kind of degradation. If capacitance measurements (CV) [1] or charge pumping technique (CP) [2] cannot provide relevant results because of geometrical issues, efforts can be done to get physical information from the linear Id-Vg curves measured during the stress, for example as the Y-function method does [3].
In this paper we focus the attention on Hot Carrier Stress (HCS), that remains one of the major reliability concerns [4], [5], in particular for flash memories [6], [7], since the programming current degradation is mainly due to hot carrier damage leading to the failure of the cell itself. Approaches proposed in literature to predict the MOSFET degradation under HCS are based on the Energy Driven Paradigm [8], [9], whose models have been calibrated on the drift of the inverse of the maximum transconductance (1/Gmmax), extracted from the linear Id-Vg characteristics. This parameter has been demonstrated to be proportional to the amount of interface traps and to the low field mobility reduction [10].
This paper explores the physical validity of Gmmax extraction together with Y-function technique and proposes a novel extraction methodology for an accurate degradation assessment whenever the device is stressed.
Section snippets
Experimental details and conventional parameter extractions
The experiments presented in this work have been done on MOSFETs belonging to the 40 nm embedded 1T-NOR flash technology developed at STMicroelectronics. These transistors have flash technology geometry (tox = 9.7 nm, W = 60 nm, L = 140 nm), and are built by shorting the control and floating gates with the objective to reproduce and study the stress suffered by the bottom part of the cell. For such geometry CP measurements do not lead to relevant results due to “geometrical effects” [11]. Two different
Limitations of conventional techniques for parameter extractions
The underlying mismatch between the conventional methodologies noticed in the previous section could come from different sources. Firstly, Y-function technique accounts for the presence of access resistance through θ1 while it is not the case for Gmmax extraction. However, it has been verified for such devices that θ1 decrease proportionally with µ0, indicating that Racc is almost constant during the stress (not shown here).
In order to investigate the validity of the extracted parameters, a
Method 1
As evidenced in Fig. 2, drain current below threshold is a good indicator of pure electrostatic drifts. However, interface defects have an amphoteric nature [14] and so one cannot easily get the Δ VthCC below threshold because of the subthreshold slope (SS) evolution with Dit (Fig. 1a). The first proposed approach is to quantify the physical degradation in a wide Vg range keeping a phenomenological model for μ(Vg) and improving the QINV(VG) from the conventionally used strong inversion
Results and discussions
The proposed extraction technique has been applied on devices having experienced HCS (as described in Section 2). In Fig. 9 the results concerning the stress condition Vg = 6 V/Vd = 4 V are shown. Looking at the electrostatic degradation, Fig. 9a, it is clear that the Vth drift is mainly driven by electrons trapped in the oxide bulk up to tstress ~ 100 ms. Afterwards, the interface traps start to play a role: SS− 1 starts to decrease and the total ΔVth becomes higher than the electrostatic shift only
Conclusions
Conventional procedures for parameter extraction applied during stress for MOSFET devices have been investigated. After having analyzed them and underlined the difficulty to correctly separate electrostatic and transport degradations occurring in the presence of interface charges, a novel technique that successfully addresses this point is presented and validated.
The experimental results obtained using the proposed methodology during Hot Carrier Stress provide deeper insights into the relation
References (17)
- et al.
Charge accumulation and mobility in thin dielectric MOS transistors
Solid State Electron.
(September 1982) - et al.
Fundamental of Modern VLSI Devices
(June 2013) - et al.
A reliable approach to charge-pumping measurements in MOS transistors
IEEE Trans. Electron Devices
(January 1984) New method for the extraction of MOSFET parameters
Electron. Lett.
(April 1988)- et al.
Hot carrier degradation in submicrometre MOSFETs: from uniform injection towards the real operating conditions
Semicond. Sci. Technol.
(September 1995) - et al.
Channel hot carrier degradation mechanism in long/short channel n-FinFETs
IEEE Trans. Electron Devices
(December 2013) - et al.
Reliability performance of ETOX based flash memories
- et al.
Reliability issues of flash memory cells
Proc. IEEE
(May 1993)
Cited by (5)
An electro-thermal parametric degradation model of insulated gate bipolar transistor modules
2020, Microelectronics ReliabilityCitation Excerpt :The electrical activity that generates heat occurs in the chip, and the heat transfer occurs throughout the whole structure of the IGBT module. The failure mechanisms at the die level include time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), bias temperature instability (BTI), electromigration (EM) [11–14], latch-up, avalanche, and secondary breakdown [15]. Among these, TDDB, HCI, and BTI are directly related to degradations in the gate.
Microscopic analysis of erase-induced degradation in 40 nm NOR flash technology
2016, IEEE Transactions on Device and Materials ReliabilityHot carrier stress: Aging modeling and analysis of defect location
2016, IEEE International Reliability Physics Symposium ProceedingsHot Carrier Stress modeling: From degradation kinetics to trap distribution evolution
2016, IEEE International Integrated Reliability Workshop Final ReportRelaxation-free characterization of Flash programming dynamics along P-E cycling
2016, IEEE International Integrated Reliability Workshop Final Report