Physically-based extraction methodology for accurate MOSFET degradation assessment

doi:10.1016/j.microrel.2015.06.063

Microelectronics Reliability

Volume 55, Issues 9–10, August–September 2015, Pages 1417-1421

https://doi.org/10.1016/j.microrel.2015.06.063 Get rights and content

Highlights

•
Conventional extractions applied for degraded MOSFETs via HCI have been explored.
•
The complexity to accurately extract the aging through IdVg has been underlined.
•
We propose a novel method that extracts easily electrostatic and transport drifts.
•
Deeper insights into the electrical impact of the trap location have been addressed.

Abstract

This paper analyzes conventional parameter extraction methodologies applied to MOSFET devices subject to electrical stress and highlights the complexity to accurately get and separate both electrostatic and transport degradations. It is shown that an accurate Coulomb scattering assessment from the linear Id-Vg characteristics is mandatory whenever the amount of interface charges/traps becomes significant. Thus, this paper proposes a novel technique able to extract the electrostatic drift and the field-dependent mobility directly from the experimental data without any a priori assumption for the transport.

Applied to MOSFETs experiencing Hot Carrier Stress, the proposed methodology provides deeper insights into the relationship between stress-induced defects location and their impact on electrostatic and transport degradations.

Introduction

The precise extraction of MOSFET parameters is a major concern for both characterization and circuit design purposes in microelectronics. With the continuous device down-scaling an accurate extraction of the physical parameters recorded as a function of the stress is fundamental to get the device behavior for any kind of degradation. If capacitance measurements (CV) [1] or charge pumping technique (CP) [2] cannot provide relevant results because of geometrical issues, efforts can be done to get physical information from the linear Id-Vg curves measured during the stress, for example as the Y-function method does [3].

In this paper we focus the attention on Hot Carrier Stress (HCS), that remains one of the major reliability concerns [4], [5], in particular for flash memories [6], [7], since the programming current degradation is mainly due to hot carrier damage leading to the failure of the cell itself. Approaches proposed in literature to predict the MOSFET degradation under HCS are based on the Energy Driven Paradigm [8], [9], whose models have been calibrated on the drift of the inverse of the maximum transconductance (1/Gm_max), extracted from the linear Id-Vg characteristics. This parameter has been demonstrated to be proportional to the amount of interface traps and to the low field mobility reduction [10].

This paper explores the physical validity of Gm_max extraction together with Y-function technique and proposes a novel extraction methodology for an accurate degradation assessment whenever the device is stressed.

Section snippets

Experimental details and conventional parameter extractions

The experiments presented in this work have been done on MOSFETs belonging to the 40 nm embedded 1T-NOR flash technology developed at STMicroelectronics. These transistors have flash technology geometry (t_ox = 9.7 nm, W = 60 nm, L = 140 nm), and are built by shorting the control and floating gates with the objective to reproduce and study the stress suffered by the bottom part of the cell. For such geometry CP measurements do not lead to relevant results due to “geometrical effects” [11]. Two different

Limitations of conventional techniques for parameter extractions

The underlying mismatch between the conventional methodologies noticed in the previous section could come from different sources. Firstly, Y-function technique accounts for the presence of access resistance through θ₁ while it is not the case for Gm_max extraction. However, it has been verified for such devices that θ₁ decrease proportionally with µ₀, indicating that Racc is almost constant during the stress (not shown here).

In order to investigate the validity of the extracted parameters, a

Method 1

As evidenced in Fig. 2, drain current below threshold is a good indicator of pure electrostatic drifts. However, interface defects have an amphoteric nature [14] and so one cannot easily get the Δ Vth_CC below threshold because of the subthreshold slope (SS) evolution with Dit (Fig. 1a). The first proposed approach is to quantify the physical degradation in a wide Vg range keeping a phenomenological model for μ(Vg) and improving the Q_INV(V_G) from the conventionally used strong inversion

Results and discussions

The proposed extraction technique has been applied on devices having experienced HCS (as described in Section 2). In Fig. 9 the results concerning the stress condition Vg = 6 V/Vd = 4 V are shown. Looking at the electrostatic degradation, Fig. 9a, it is clear that the Vth drift is mainly driven by electrons trapped in the oxide bulk up to t_stress ~ 100 ms. Afterwards, the interface traps start to play a role: SS^− 1 starts to decrease and the total ΔVth becomes higher than the electrostatic shift only

Conclusions

Conventional procedures for parameter extraction applied during stress for MOSFET devices have been investigated. After having analyzed them and underlined the difficulty to correctly separate electrostatic and transport degradations occurring in the presence of interface charges, a novel technique that successfully addresses this point is presented and validated.

The experimental results obtained using the proposed methodology during Hot Carrier Stress provide deeper insights into the relation

References (17)

C.G. Sodini et al.
Charge accumulation and mobility in thin dielectric MOS transistors
Solid State Electron.
(September 1982)
Y. Taur et al.
Fundamental of Modern VLSI Devices
(June 2013)
G. Groeseneken et al.
A reliable approach to charge-pumping measurements in MOS transistors
IEEE Trans. Electron Devices
(January 1984)
G. Ghibaudo
New method for the extraction of MOSFET parameters
Electron. Lett.
(April 1988)
G. Groeseneken et al.
Hot carrier degradation in submicrometre MOSFETs: from uniform injection towards the real operating conditions
Semicond. Sci. Technol.
(September 1995)
M. Cho et al.
Channel hot carrier degradation mechanism in long/short channel n-FinFETs
IEEE Trans. Electron Devices
(December 2013)
G. Verma et al.
Reliability performance of ETOX based flash memories
S. Aritome et al.
Reliability issues of flash memory cells
Proc. IEEE
(May 1993)

There are more references available in the full text version of this article.

Cited by (5)

An electro-thermal parametric degradation model of insulated gate bipolar transistor modules
2020, Microelectronics Reliability
Citation Excerpt :
The electrical activity that generates heat occurs in the chip, and the heat transfer occurs throughout the whole structure of the IGBT module. The failure mechanisms at the die level include time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), bias temperature instability (BTI), electromigration (EM) [11–14], latch-up, avalanche, and secondary breakdown [15]. Among these, TDDB, HCI, and BTI are directly related to degradations in the gate.
Insulated gate bipolar transistor (IGBT) is widely used in a variety of applications, many of them are safety-critical. The failure of the IGBT accounts for a significant portion of the failures in the converter. An electro-thermal model is useful for predicting the junction temperature in power electronic components and modules. The model parameters change with degradation, but parameters of such models are not readily available in the literature or in the parts documentation. In this work, various combinations of parameters, source voltage, junction temperature, gate voltage, collector current, gate resistance, and frequency are developed and executed, and the electro-thermal model parameters are derived from these experimental results. The change of switching power loss and thermal resistance with degradation is derived from accelerated aging experiments that combine temperature and current. The results show that degradation in the thermal resistance over a period of 9000 cycles can increase the junction temperature by more than 20% compared with the original junction and case temperature difference. Degradation at the die level can cause a 50% increase in the switching power loss compared with the original switching power loss under the same working conditions. The electro-thermal model and parametric degradation model are applied in the sine pulse width modulation (SPWM) simulate circuit to improve the accuracy of temperature prediction after degradation.
Microscopic analysis of erase-induced degradation in 40 nm NOR flash technology
2016, IEEE Transactions on Device and Materials Reliability
Hot carrier stress: Aging modeling and analysis of defect location
2016, IEEE International Reliability Physics Symposium Proceedings
Hot Carrier Stress modeling: From degradation kinetics to trap distribution evolution
2016, IEEE International Integrated Reliability Workshop Final Report
Relaxation-free characterization of Flash programming dynamics along P-E cycling
2016, IEEE International Integrated Reliability Workshop Final Report

View full text

Physically-based extraction methodology for accurate MOSFET degradation assessment

Highlights

Abstract

Introduction

Section snippets

Experimental details and conventional parameter extractions

Limitations of conventional techniques for parameter extractions

Method 1

Results and discussions

Conclusions

Solid State Electron.

Fundamental of Modern VLSI Devices

A reliable approach to charge-pumping measurements in MOS transistors

IEEE Trans. Electron Devices

New method for the extraction of MOSFET parameters

Electron. Lett.

Hot carrier degradation in submicrometre MOSFETs: from uniform injection towards the real operating conditions

Semicond. Sci. Technol.

Channel hot carrier degradation mechanism in long/short channel n-FinFETs

IEEE Trans. Electron Devices

Reliability performance of ETOX based flash memories

Reliability issues of flash memory cells

Proc. IEEE