Design of SET tolerant LC oscillators using distributed bias circuitry
Introduction
CMOS RF integrated circuits are actively being explored for use in radiation environments, such as space applications. Particularly, LC-tank voltage-controlled oscillators (VCOs) used for frequency synthesizers require special attention, as the effects of single event transients (SETs) decay slowly due to slow settling behavior of phase-locked loops. Radiation strikes generate significant spurious spectral components, which lead to interference with other channels in RF transceivers. In high frequency circuits, smaller node capacitances result in large node voltage changes for given SET induced charges. Moreover, CMOS technology scaling has led to lower supply voltages, and thus, reduced charge oscillating in the LC-tanks of the VCOs. As a result, high frequency VCOs are more vulnerable to SETs in high energy radiation environments [1]. Hence, improving radiation tolerance to SETs for high frequency VCOs is very important.
The SET response in LC-tank VCOs has been studied earlier [1], [2], [3]. The output and the bias transistor nodes of these VCOs are found to be most sensitive to SET effects [2], [3]. The output transistor nodes in NMOS-cross coupled VCOs can be made SET tolerant by including PMOS cross-coupled loads [3]. SET sensitivity at the output transistor nodes can be further reduced by using quadrature phase oscillators at the expense of extra power consumption [1], [4]. The bias transistor nodes of these VCOs require further attention to improve SET tolerance under radiation environment.
The sensitivity to SET at the bias transistor nodes can be reduced by operating the oscillator at high power as shown for a current starved ring VCO [5]. However, due to their poor phase noise, ring VCOs are generally not used for RF applications. Another way to minimize SET effects on the bias circuitry is to isolate the circuitry by adding a decoupling resistor in series with the bias current transistor [2]. However, the decoupling resistor value cannot be too high and is limited by the voltage headroom, which limits the improvement achieved by adding the resistor.
In this paper, a distributed biasing scheme is proposed to achieve high SET tolerance at the bias transistor nodes, while overcoming the two limitations listed above. The proposed scheme achieves significant improvement in SET tolerance as compared to a VCO with bias decoupling resistor, without an increase in power consumption or degradation in phase noise.
Section snippets
Improvement in SET tolerance in LC-tank oscillators
Fig. 1a shows the LC–VCO with a single bias resistor (VCO–SBR) reported in [2]. The decoupling resistor (R1) in the bias current path reduces SET effects on VCO output when radiation strike occurs at the drain of the bias transistor. The resistor R1 adds isolation between the bias current source and the LC-tank in the oscillator. As shown in Fig. 1a, the output impedance looking from drain of the bias transistor (Mb) increases when decoupling resistor R1 is added. Hence, a larger fraction of
Proposed SET tolerant scheme for bias circuitry
Fig. 1b illustrates the proposed SET tolerant VCO with distributed bias resistors (VCO–DBR). It uses a distributed bias current source. The bias current source employs n parallel bias transistors, each having a decoupling resistor in series with it. In VCO–DBR, the channel width of each bias transistor is (1/n)th of the channel width of VCO–SBR bias transistor, and each decoupling resistor is n times VCO–SBR's decoupling resistor. Therefore, the current flowing through each bias current source
Simulation results for SET tolerance
The LC-tank VCOs were designed with a center frequency of 14 GHz in a standard UMC 90 nm CMOS technology using Cadence design environment. The SET tolerance of these VCOs was simulated using SET current modeled by a double exponential current pulse [1]. The radiation strike at the reverse biased drain region of the bias transistor generates SET current, which consists of an impulse drift current followed by diffusion current. Fig. 5 shows the injected double exponential SET current pulse (ISET)
Conclusion
The SET effect on the bias current transistor node of an LC-tank VCO, and its mitigation techniques have been discussed in this paper. We have proposed a VCO with distributed bias circuitry (VCO–DBR) to reduce phase errors caused in the VCO due to radiation strikes. The distributed biasing technique exploits the effect of variation in bias current MOS transistors with drain-source voltage to improve SET tolerance. Circuit simulation results of the proposed VCO–DBR (with 14 GHz center frequency)
Acknowledgment
The authors would like to thank SAC-Ahmedabad, ISRO, for funding the project and Mr. CVN Rao for fruitful discussions.
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