Power cycling issues and challenges of SiC-MOSFET power modules in high temperature conditions

Highlights

• Main experimental difficulties to perform power cycles of SiC-MOSFET devices

• Tentative to minimize tunneling effects has been implemented.

• A proposal to implement power cycles with an intermediate gate bias condition

Abstract

Silicon carbide (SiC) MOSFETs power modules are very attractive devices and are already available in the market. Nevertheless, despite technological progress, reliability remains an issue and reliability tests must be conducted to introduce more widely these devices into power systems. Because of trapping/de-trapping phenomena at the SiC/SiO₂ interface that lead to the shift of threshold voltage, test protocols based on silicon components cannot be used as is, especially in high temperature conditions. Using high temperature SiC MOSFET power modules, we highlight the main experimental difficulties to perform power cycling tests. These reversible physical mechanisms preclude the use of temperature sensitive parameters (TSEP) for junction temperature measurements, so we set up fiber optic temperature sensors for this purpose. Moreover, these degradation phenomena lead to difficulties in both controlling the test conditions and seeking for reliable aging indicator parameters. Finally, a power cycling test protocol at high temperature conditions is proposed for such devices.

Introduction

Silicon Carbide (SiC) MOSFETs are very attractive devices for high power applications allowing high frequency and high temperature operations [1]. Their intrinsic material properties enable them to overcome the physical limits of silicon-based devices [2] and to allow the development of highly integrated and efficient power systems with reduced cooling systems. If these devices are welcome for railway and automotive applications to increase the energy efficiency, they are needed for aeronautical applications in areas where severe conditions may occur.

Several SiC power MOSFET modules are already available in the market, nevertheless, despite technological progress, reliability remains an important issue. One of the major reliability concerns electrical instabilities due to charge trapping and de-trapping mechanisms at the SiC/SiO2 interface and in its vicinity in the oxide material [3], [4], [5], [6]. As direct consequence, the threshold voltage (V_T) is affected by positive or negative shifts depending on gate voltage bias [7], [8]. A positive gate bias stress leads to a positive shift of the threshold voltage (i.e. an increase of V_T), otherwise, a negative gate bias results in a negative shift of the threshold voltage (i.e. a decrease of V_T). As indirect consequence, the on-state resistance (R_DSON) increases or decreases depending on whether there is a positive or negative shift on V_T, respectively.

Even though these mechanisms also occur in Silicon MOSFETs devices, their occurrence is so rare that they are practically undetectable. This is due to the higher band gap of the SiC, comparatively to the silicon, that leads to a decrease of the conduction band offset between the semiconductor crystal and the SiO2 at the interface ending up in a more significant tunnel effect. These tunnel effects are responsible of the charge trapping (or de-trapping) from the channel and the gate oxide. These mechanisms are perfectly reversible as well as their effects in the voltage threshold shifts. They are dependent on several parameters including the duration and magnitude of the gate bias and the temperature.

Beyond the intrinsic reliability problems of the gate oxide and the die itself, these phenomena make difficult the traditional approach to reliability testing of the technology, interconnection, assembly and packaging of these devices. Power cycling reliability protocols for silicon devices cannot be transposed as is for SiC devices with insulated gate structure such as MOSFETs. As these phenomena are strongly amplified with temperature, estimation of the reliability of power modules technologies for high temperature applications (beyond 175 °C) remains an open issue.

Some papers deal with reliability testing in high temperature conditions. Among them, high temperature gate bias (HTGB) or time-dependent dielectric breakdown (TDDB) tests at 150 °C or 175 °C are addressed [9], [10], [11] and issues when using Joint Electron Devices Engineering Council (JEDEC) standards are discussed. In [12], power cycling tests on TO-247 package SiC-MOSFETs are investigated at 75 °C reference temperature where gate oxide characteristic shifts don't occur.

This paper is an attempt, based on experimental tests, to fill a gap concerning power cycling tests in high temperatures conditions of SiC-MOSFETs. After a description of the traditional approach of power cycling tests in DC mode for silicon based devices, we will highlight the main experimental difficulties related to reliability testing of MOS-gated SiC devices in high temperature environment. For this purpose, high-temperature silicon carbide (SiC) Half-Bridge MOSFET Power Modules have been used. Finally, a test protocol will be proposed.