Elsevier

Microelectronics Reliability

Volume 57, February 2016, Pages 24-33
Microelectronics Reliability

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

https://doi.org/10.1016/j.microrel.2015.12.004Get rights and content

Highlights

  • A threshold voltage model for GeOI/GeON MOSFET is built in good agreement with the experimental data and other models.

  • A good trade-off among the MOSFET characteristics can be obtained using the model.

  • Effects of device parameters on threshold voltage degradation are discussed in detail.

Abstract

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.

Introduction

With continuous downscaling of metal-oxide-semiconductor field-effect transistor (MOSFET), its gate oxide becomes thinner, resulting in unacceptably high gate leakage current. Therefore, high-k dielectric materials, e.g. Al2O3 [1], HfO2 [2], and ZrO2 [3], are used as the gate dielectric of MOSFETs to allow the use of thicker gate dielectric and thus suppress the gate leakage current. On the other hand, due to the higher carrier mobility of Ge than Si [4], Ge has been proposed as a promising channel material for MOS devices. However, Ge CMOS device is more susceptible to short-channel effect (SCE) due to the high permittivity of Ge [5] and strong fringing-field effect (FFE) that resulted from high-k gate dielectric [6]. To overcome these issues, MOSFETs with ultra-thin-body (UTB) and thin buried oxide are proposed as a promising device structure for high-speed circuits with 10-nm-order gate length [7] because the structure holds high immunity to threshold-voltage variability and better control of SCE [8], [9], [10]. As an important electrical parameter, the threshold voltage of the devices has been studied extensively. Fasarakis et al. [11] and Manan et al. [12] developed 2-D threshold-voltage models for SOI (silicon-on-insulator) and SON (silicon-on-nothing) MOSFETs, but Ge channel was not involved. Hu et al. [13] proposed a model to account for the sub-threshold performance of UTB Ge MOSFETs, but threshold voltage and high-k gate dielectric were not considered. Although Fan et al. [14] established a threshold-voltage model for GeOI MOSFET, the k value of the buried insulator was not taken into account. Therefore, it is necessary and significant to establish a threshold-voltage model to investigate the impacts of high-k gate dielectric and low-k buried insulator on the threshold characteristics of UTB germanium-on-insulator (GeOI) MOSFET and UTB germanium-on-nothing (GeON) MOSFET.

In this work, the surface potential of GeOI and GeON MOSFETs with high-k gate dielectric is obtained by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions, and as a result, the threshold-voltage model is derived. The model is also applicable for UTB SOI MOSFET and UTB SON MOSFET through changing the channel material to silicon (i.e. setting the relevant parameters to those of Si). The validity of the model is confirmed by comparing with experiment data [15] and the full-depleted SOI (FDSOI) MOSFET model [15]. To further confirm the validity of the model, sub-threshold swing is also derived based on the surface potential and the simulated results for GeON MOSFET exhibit good consistence with the results of technology computer-aided design (TCAD) simulation [16]. The influences of some structural and physical parameters on the threshold behavior are discussed. It is found that owing to enhanced FFE, the threshold-voltage roll-off is degraded if high-k material replaces SiO2 as gate dielectric. This degradation can be alleviated by using buried insulator with low dielectric constant, which can theoretically explain why the threshold behaviors of SON and GeON MOSFETs are better than those of SOI and GeOI counterparts respectively.

Section snippets

Model derivation

A schematic diagram of the UTB MOSFET with buried-insulator is shown in Fig. 1. The buried insulator exists between the Ge channel and substrate. The x axis is along the channel direction, starting at the edge of the source, and the y axis is perpendicular to the channel, starting at the gate-dielectric/channel interface. The gate electrode is heavily-doped polysilicon or metal. The source and drain with lightly-doped extension regions are used for suppressing the hot-carrier effect. If the

Results and discussion

Besides the permittivities of the gate dielectric and buried insulator, the dielectric constants and intrinsic carrier concentration of the channel material are also included in the above model. In other words, the model is applicable to SOI device too. So, the simulated threshold voltage is first compared with experimental data of SOI device with polysilicon gate [15]. As shown in Fig. 2(a), the simulated results at tch = 80 nm and L <~ 800 nm are consistent with the experimental data, indicating

Conclusion

The surface potential of GeOI and GeON MOSFETs with high-k gate dielectric is derived. Based on the potential distribution, a threshold-voltage model is built. The simulated results match well with experimental data and the FDSOI model, confirming the validity of the model. Also, the sub-threshold swing is derived based on the potential distribution, and the simulated results exhibit good agreement with those of TCAD. Using the model, the influences of gate-dielectric permittivity,

Acknowledgments

This work is financially supported by the National Natural Science Foundation of China (grant nos. 61274112, 61176100, 61404055), Hubei Provincial Department of Education Scientific and Technological Research Projects (grant no. B2013263), the University Development Fund (Nanotechnology Research Institute, 00600009) of the University of Hong Kong and the Hong Kong Polytechnic University (project number: 1-ZVB1).

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