Invited paperThe impact on power semiconductor device operation due to local electric field alterations in the planar junction termination
Introduction
In the past few decades, the power electronics revolution has opened up a wide range of possibilities in terms of controlling the way electrical energy is transported and used. At the heart of this revolution are power semiconductor devices which are in general terms covering an ever increasing number of applications and are experiencing continuous improvements in their performance and reliability. The main technology development trend in power devices has always been focused on increasing the power ratings while also improving the overall device performance in terms of reduced losses, increased robustness, better controllability and in particular, reliable behaviour under normal and stress/fault operational conditions. High voltage power semiconductors differ from their low voltage counterparts in a number of structural and design aspects as shown in Fig. 1. In addition to the active area region which basically defines the device concept “diode, Thyristor, MOSFET, IGBT, etc.” [1], they include:
- 1-
the bulk region having a wide and low doped base “drift” layer to support the electric field required for the high voltage ratings
- 2-
the junction termination (JT) region to shape the pn junction edge and surface profile for obtaining a controlled electric field distribution and the maximum possible reverse voltage blocking capability.
In relation to the topic of this paper, the JT region plays a critical role in all device operational modes except during the on-state conduction. During static blocking (reverse bias), turn-on and turn-off switching and under special overload and fault protection conditions, high voltages are applied across the device. Therefore, the design and protection of the JT region play a very important role in ensuring uniform and controlled electric field profiles for maintaining breakdown voltage capability under all operational conditions.
The main target of this work was to investigate the impact of possible local electric field modifications in planar JT regions on the device blocking capability. Planar JT designs are employed for the majority of modern power semiconductors such as IGBTs or diodes and also for silicon carbide based devices including MOSFETs and diodes. It is important to point out that the findings can also be applicable to non-planar JT concepts as described below.
Section snippets
Power device junction termination and passivation
Over the past few decades and in line with the advances made in power semiconductor devices and materials, a wide range of junction termination and passivation concepts have been proposed, developed and implemented. In brief, two main design principles have been employed as follows [2]:
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mesa/bevel edge etching which is widely used in bipolar devices such as diodes and thyristors [3]
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planar designs including floating guard rings (GR) [4] with or without field plates or junction termination
Local alteration in the electric field profile
Most of the design and optimization work carried out in the past with regard to the JT design and performance does not take into account the possible local alteration in the electric field profile with respect to the whole junction termination region. Before providing more insight into this aspect, we must outline the possible mechanisms and causes that could result in such a localized modification. As outlined previously, the main factors determining the electric field profiles are the JT pn
TCAD simulation results
The ideal simulation method to better understand the impact of a localized change in the electric field is to employ 3D device models for the junction termination region. A first attempt in this direction was carried out for the 1700 V structure discussed previously. The modification in the electric field was conceived by adjusting the surface charge value for a section of the JT region as shown in Fig. 6 at 1250 V and 25 °C. The modified region exhibited a more positive surface charge (5e11/cm3)
Experimental results
The results obtained from the simulation results have been verified experimentally on 6.5 kV IGBTs by the addition of a controlled field plate by means of masking and etching and in similar locations to those studied by simulations. Two different field plate designs having small (20 μm × 100 μm) and large (30 μm × 300 μm) dimensions were employed at two angles (90° and 45° tilted with respect to the VLD junction edge) to evaluate their impact on the device performance. Fig. 11 shows the small field
Further improvements
Both simulations and experiments point in the direction of junction termination sensitivity to locally modified electric field profiles and the importance for understanding their impact on device performance. Today, locally modified electric fields are more likely to arise due to operational conditions under humidity, high temperatures and high voltages. For example, such conditions could result in ion migration within the module and adversely affect the surface charge on the junction
Conclusion
This paper discussed the impact of locally modified electric field profiles in the planar junction termination region for power semiconductor devices. Such issues could arise from potential extrinsic causes related to manufacturing, operational or environmental influences and are shown to have a critical influence on the power device behaviour with respect to the voltage blocking capability and reliability.
Acknowledgments
The authors wish to thank A. Mukhitdinov and C. Toker-Bieri for the preparation of the metal field plate experiments.
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