A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits

https://doi.org/10.1016/j.microrel.2016.01.001Get rights and content

Highlights

  • A compact model is proposed to simulate the mechanism of charge trapping and release in MOSFET devices.

  • Trap state is treated by a Markov process and governed by a differential equation that can be solved by a SPICE-like simulator.

  • Electric input stimulus can be a general transient signal without clear cycles of stress and recovery, unlike the assumption of many models in the state of the art.

  • Statistical variability in trap parameters is considered in the model.

  • An operational amplifier is simulated using the new model and the proposed approach is compared with the state of the art.

Abstract

A compact add-on model is proposed to simulate the mechanism of charge trapping and release (detrapping) and its effect on the threshold voltage of MOSFET devices. The model uses implicit algebraic differential equations compatible with transient analysis in SPICE. It also shares the accuracy level of the transient analysis. A micro-model approach is used, and each trap is treated by a two-state Markov process. The normalization of trap behavior can be enabled or disabled, so that the designer can compare average trap behavior to the result of repeated Monte-Carlo simulations of a circuit. In this manner, the model can compromise between device-level modeling and circuit-level modeling. Unlike models geared towards digital circuit design, the trapping and release rates need not be constant during electrical stress. The trapping and release rates are a function of time, as they depend on the circuit state-space equations. An operational amplifier is analyzed using the new model, and the proposed approach is compared with the state of the art.

Introduction

Many problems have arisen in analog circuit design due to metal-oxide-semiconductor field-effect transistor (MOSFET) downscaling. One important mechanism to consider is the trapping and release of free charge carriers (conduction band electrons, n, or valence band holes, p) from the channel region, and its affect on the gate voltage required to reach the threshold condition (Vth) [1], [2], [3], [4], [5].

Trap locations are caused by defects or impurities inside the MOSFET gate insulator or the substrate–insulator interface (Si–SiO2). The gate insulator is SiO2 in traditional MOS devices, but is often a composite of stacked layers in newer technologies [6], [7]. Possible trap energy levels are distributed within a range, but lie within the silicon bandgap. According to the literature on carrier transport, the expected number of occupied trap locations (N oc ) is temperature (T) dependent and is a function of the strength and history of the electrical field over the gate. In recent technology nodes, channel doping concentration (NDEP) was increased to counter short-channel effects in shrinking devices. When combined with the use of High-K dielectrics to decrease effective oxide thickness (TOXE) and check leakage current, this results in a large electric field over the gate oxide when a gate-to-source voltage (Vgs) and a drain-to-source voltage (Vds) are applied [8].

Over short windows of time, often at the scale of transient signal propagation, the trapping and release of charge carriers can result in Vth fluctuation [9], and appear as a random telegraph signal (RTS) in measurements of drain-to-source current (Ids) [10], [11]. Over longer timescales, a large electric field can cause a significant change, ΔVth , in effective threshold voltage, as the number of occupied trap locations dominates over the unoccupied traps. This is the cause of the bias temperature instability (BTI) mechanism [12], [13], [14], [15]. If the circuit is turned off or the supply voltage is scaled down for a measure of time, then the average number of occupied traps will decrease. This measure of time denotes a recovery cycle [16]. In general, the change Δ Vth is proportional in magnitude to N oc .

The analog designer cannot control MOSFET NDEP and TOXE, unless a different choice of device is available in the technology design kit. The designer does have control over the electrical field through control of the circuit node voltages, terminal currents, and device dimensions. It is therefore important to model the effect of trapping and release on device behavior during circuit simulation [17].

Trap modeling can be done using technology computer-aided design (TCAD). Simulation of 3D electrostatics and doping-induced variability gives accurate predictions [14], [18], [10]. Some issues remain for the designer to consider:

  • (I)

    The computational cost of TCAD simulation is large. The designer is interested in the simulation of a complete circuit comprised of tens or hundreds of devices.

  • (II)

    Limited availability of TCAD-based compact models. Compact models derived from a TCAD model, including trap dynamics, are one solution to (I) above. They capture key behavior and trade accuracy for speed [19]. However, they are often unavailable to the designer. At this time, BSIM4 MOSFET models are commonly provided by most technology foundries for circuit simulation [20]. BSIM4 does not include a suitable model for RTS or BTI.

A compromise solution to the issues raised above is to add new circuit components to complement the MOSFET model and model charge trapping and release. Model equations can be written in a language compatible with the circuit simulator. For example, VerilogA [21] can be used to write a time-varying ΔVth model, then series connected with each MOSFET gate as shown in Fig. 1. In addition to fast simulation, the advantage of such models is simplicity. No model order reduction is used and model equations are readable and adjustable by the designer without reference to TCAD tools. Disadvantages are as follows:

  • (I)

    Limited capability of circuit simulators. Numerical simulators, such as SPECTRE [22], are restricted to lumped elements and certain conductor models, and solve algebraic differential equations in time only. This is part of the compromise between speed and accuracy.

  • (II)

    Opaque compact models with inaccessible internal variables. For example, the Fermi level of a charge carrier at a point along the channel is inaccessible as an output of the BSIM4 model, but is needed to describe a trap state. As a result, some of the MOSFET equations must be duplicated from BSIM4 documentation, which may be error prone or slow down circuit simulation.

  • (III)

    Additional data is needed to fit a compact trap model. Associated with the traps are a number of parameters that need to be defined, such as trap energy levels. Parameters may be statistical with a distribution of values.

A compact model is described for charge trapping and release during transient simulation, and its effect on Vth:

  • (I)

    A micro-model approach is used. The state of each trap (empty/full) is treated individually by a Markov process and governed by a linear differential equation. Stochastic analysis is possible with the proposed model, and the designer can compare average Vth instability with repeated Monte-Carlo simulations. This is done in Section 2.1.

  • (II)

    A flexible time-domain model is proposed. Unlike models geared towards digital circuits, the trapping and release rates are not constant during simulation, but can be time-dependent — depending on the circuit state-space equations. Instead of a predefined analytical solution, the differential equation for trap state is solved concurrently and numerically with the circuit state-space equations during transient analysis. Solution stability and accuracy are handled by the simulator. This is discussed in Section 2.3.

  • (III)

    The effect of Vds, poly-gate depletion potential (ψp), surface potential (ψs), and other details are taken into account in the calculation of charge trapping and release rates. This is represented by Eq. (9) in Section 2.2. MOSFETs in analog circuits may operate in saturation with | Vds | > 0. This mitigates charge trapping as the electrical field is weaker at the drain compared to the source. In models geared towards digital design, a simplified model is often used that considers only Vgs. The effect of Vds is neglected [4], [16], or added with a fitting parameter [23].

  • (IV)

    The proposed trap model is simple and is easily adjusted to include statistical variability in trap parameters. This is done with a simple parameterization of the trap differential equation in Section 3.

In Section 4, the new model is used to simulate an example circuit with comparisons to state of the art models.

Section snippets

Two-state capture and release representation

Each trap can capture or release a charge carrier. This is governed by a two-state process: a full trap is defined to be in state 1, while an empty trap is in state 0. Capture and release are defined by two time constants τ c  and τ e  for each trap.

The conditional probability of state 1 at time t, given state 0 at time 0 is denoted by the function P 1/0 (t),

and calculated by solving a differential equation [11]1:Ṗ1/0t=τc1τc1+τe1P1/0t.

The

Extraction of distributed trap parameters

Values σ 0 , ΔE B , ECox - E t , x t , and y t  are needed to fit Eq. (8). They require information beyond what is included in the MOSFET model. Their variation may account for the joint distribution of fast and slow traps under fixed bias and temperature conditions [5], [27]. For example, in [5, Fig. 8] measurement data for the joint distribution of (τ c , τ e ) under fixed ( Vgs, Vds, T ) is collected by tailed experimental time-dependent defect spectroscopy (TDDS).

Below, a procedure is proposed to seamlessly

Example with comparison to the state of the art

The operational amplifier (opAmp) shown in Fig. 3 is used as a circuit example. It consists of 16 MOSFETs, modeled using BSIM4 models and a 45 nm technology [28]; I ref  = 5 μA , C load  = 10 pF , and Vdd = Vss = 800 mV.The MOSFETs are sized, so that the fresh opAmp (at t = 0) is stable with suitable open-loop gain and bandwidth, as well as suitable slew rate and input and output swings in consideration of the input signal, Vin, that will be applied. The opAmp is connected as a voltage follower. Each MOSFET is

Conclusions

A model was described for charge trapping and release in MOSFETs, so as to predict the threshold voltage change in response to an arbitrary transient input signal.

The model holds the state of each trap in the form of the differential equation for the probability of trap occupancy. The model is simple and easily adjusted to incorporate statistical variability in trap parameters. It showed promising performance when compared to the state of the art in the simulation of an operational amplifier.

References (30)

  • S.M. Amoroso et al.

    RTN and BTI in nanoscale MOSFETs: a comprehensive statistical simulation study

    Solid State Electron.

    (2013)
  • V.B. Kleeberger

    A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits

    Microelectron. Reliab.

    (2014)
  • M. Uren et al.

    Noise in submicron mosfets-a tool for characterising the Si–SiO2 interface

  • M.J. Kirton et al.

    Individual defects at the Si:SiO2 interface

    Semicond. Sci. Technol.

    (1989)
  • H. Lee et al.

    Accurate extraction of the trap depth from RTS noise data by including poly depletion effect and surface potential variation in MOSFETs

    IEICE Trans. Electron.

    (2007)
  • G. Wirth et al.

    Statistical model for MOSFET bias temperature instability component due to charge trapping

    IEEE Trans. Electron Devices

    (2011)
  • T. Grasser

    Analytic modeling of the bias temperature instability using capture/emission time maps

  • H.-J. Cho et al.

    Observation of slow oxide traps at MOSFETs having metal/high-k gate dielectric stack in accumulation mode

    IEEE Trans. Electron Devices

    (2010)
  • Y. Liu et al.

    Modeling of charge trapping induced threshold-voltage instability in high-κ gate dielectric FETs

    IEEE Electron Device Lett.

    (2006)
  • G. Gielen et al.

    Analog circuit reliability in sub-32 nanometer CMOS: analysis and mitigation

  • C. Monzio Compagnoni et al.

    First detection of single-electron charging of the floating gate of NAND flash memory cells

    IEEE Electron Device Lett.

    (2015)
  • R. da Silva et al.

    Logarithmic Behavior of the Degradation Dynamics of Metal-oxide-semiconductor Devices

    (2010)
  • T. Grasser

    Recent developments in understanding the bias temperature instability

  • W. Wang

    Compact modeling and simulation of circuit reliability for 65 nm CMOS technology

    IEEE Trans. Device Mater. Rel.

    (2007)
  • S. Markov et al.

    Statistical interactions of multiple oxide traps under BTI stress of nanoscale MOSFETs

    IEEE Electron Device Lett.

    (2013)
  • Cited by (0)

    View full text