Elsevier

Microelectronics Reliability

Volume 58, March 2016, Pages 12-16
Microelectronics Reliability

Electro-thermal simulation of current sharing in silicon and silicon carbide power modules under short circuit condition of types I and II

https://doi.org/10.1016/j.microrel.2016.01.010Get rights and content

Highlights

  • Current sharing

  • Electro-thermal compact modelling

  • Silicon and Silicon

  • Carbide IGBT and MOSFET modules

  • Short circuit of types I and II

Abstract

Current sharing during short circuit events of types I and II has been investigated by electro-thermal compact simulation of semiconductor devices paralleled in a 650 V power module. The response of silicon IGBTs has been compared to that of silicon carbide MOSFETs. The study of current unbalance due to symmetrical and asymmetrical interconnect topologies has been followed by isothermal and full electro-thermal simulation of the power modules. It has been shown that replacing in the simulation the active devices within the module by resistors leads to misleading results, because the current unbalance under short circuit conditions is mainly due to the difference in the gate-source/gate-emitter voltage among the individual paralleled devices. Finally, it has been demonstrated that in the investigated power modules, self-heating contributes to the mitigation of current unbalance.

Introduction

IGBT power modules have been developed to face the increasing demand for high-power conversion. Multiple IGBT devices are mounted within a module in parallel both to achieve higher current densities and to reduce losses. As switching speed and current densities get higher than those encountered in today's devices, proper current balancing among paralleled chips within a power module becomes a critical issue. Therefore, current balancing is an unavoidable challenge to be tackled to increase current density and for safe power switching in silicon and wide band gap devices. When it comes to the investigation of current balancing under large current switching, electro-thermal simulation is mandatory, since current sharing within the devices in a module is strongly affected by the local temperature and this dependency becomes even stronger at high current density levels.

Several investigations [1], [2], [3], [4] have been published in the past dealing with various switching conditions. Present paper focuses on the electro-thermal simulation of current sharing among paralleled chips for harsh switching modes, in particular under the short-circuit conditions of types I and II (SC I, SC II). All simulations have been carried by assuming five paralleled devices assembled in a representative power module. The components that have been considered in this investigation are a 650 V–300 A silicon IGBT power module [5] and a power module consisting of five paralleled 650 V–30 A silicon carbide MOSFETs [6]. Simulation tools and procedures are defined in Section 2. In Section 3, the effect of the module terminals and of the related parasitic inductances on current sharing is investigated by isothermal simulation of a symmetrical and of an asymmetrical topology, where the active devices have been replaced in the compact model by equivalent resistors. In Section 4, the parasitic inductances of the asymmetric module are extracted by electromagnetic simulation and the current sharing among the active devices is calculated by full electro-thermal circuit simulation.

Section snippets

Modeling and simulation

Following investigations combine 3D CAD modeling, 3D electro-magnetic simulations, and electro-thermal coupled circuit simulations. The 3D module geometry shown in Fig. 1 has been modeled by Ansys DesignModeler [7]. Parasitic inductances and resistors have been extracted by 3D electro-magnetic simulation with the Ansys Q3D Extractor tool [8].

Ansys Simplorer [9] has been used to build and calibrate the electro-thermal compact models of the silicon IGBT and SiC MOSFET based on the Basic Dynamic

Effect of terminal positions

The topology of power terminals is considered to have large impact on current sharing within a module, because the position of the individual chips strongly influences the impedance balance among the devices. Fig. 3a and b shows the different layouts considered for this investigation. The first is a symmetrical design, where the switching devices are placed symmetrically with respect to source-sink axis. This is expected to be an ideal layout in terms of current balancing. The second case deals

Full electro-thermal simulation

The aim of the simulation carried out in Section 3 was just to investigate the effect of the topology of the interconnects on the current sharing among ohmic loads replacing the active devices. In present Section, the interaction of the asymmetric module layout with the semiconductor devices is studied in detail. The main difference with previous simulation is that the current flowing through the individual devices is not only given by the voltage drop across the device, but it is also a strong

Summary and conclusions

Current unbalance in Si IGBT and SiC MOSFET power modules under SC I and SC II conditions has been investigated by means of compact modeling and electro-thermal circuit simulation. Parasitics have been extracted successfully by 3D electromagnetic simulation of a 3D CAD model of the module with symmetric and asymmetric layout. Compact models of the semiconductor devices have been developed and calibrated based on datasheet parameters. It has been shown that simplified approaches, where the

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