High-resolution wide-band LC-VCO for reliable operation in phase-locked loops☆
Introduction
Phase-locked loops (PLLs) are a basic building block in a great number of applications. Its operation achieves the synchronization of an oscillator embedded in the integrated circuit (IC) with a very stable external timing reference, typically a crystal oscillator, and for this reason the control voltage of a PLL carries very precise information about the effect of process, voltage and temperature (PVT) variations in the operation of the IC. In this respect, there is an increasing interest in the deployment of integrated PLLs along with both digital and RF circuits to provide information about the effect of PVT variations to correct it, thus increasing the robustness and reliability of the system. For instance, in [1] an on-chip PLL is used to generate the adaptive body bias in an RF power amplifier, minimizing the effect of PVT variations on its performance. A key parameter to evaluate the performance of PLLs, and therefore their suitability for sensing applications, is its phase noise.
The phase noise of PLLs is strongly related to the phase noise of the voltage-controlled oscillator (VCO) in the PLL. For this reason, resonant LC-VCOs are preferred over ring VCOs for the design of PLLs due to their better phase noise performance. Nevertheless, the phase noise of a PLL also shows a tight dependency on the frequency tuning gain of the oscillator (KVCO) [2]. In particular, as KVCO increases, any ripple present at the control voltage of the VCO translates to greater frequency variations on its output signal and thus to and increase of the phase noise of the PLL, which has a negative effect on its performance and reliability.
The frequency tuning of an LC-VCO is carried out modifying the capacitance of an MOS varactor, whose variation is around 10% of its nominal value. Because the oscillation frequency of an LC-VCO is given by , where L and Care, respectively, the equivalent inductance and capacitance of the resonant LC-tank, the 10% variation in C translates into a 5% variation in fosc, which is not wide enough to guarantee reliable operation under process, voltage and temperature (PVT) variations, and therefore demands the implementation of specific techniques to increase it. On the other hand, achieving a wide continuous frequency variation is not desirable either because it would magnify the ripple in the control voltage, resulting in an increase in phase noise and therefore in higher output jitter.
For these reasons, the most commonly used technique to widen the frequency range of LC-VCOs consists in adding a set of switched capacitors in parallel to the MOS varactor (Fig. 1a). If the capacitance of the elements in the switched capacitor bank are scaled in powers of 2, their contribution of the total LC-tank capacitance is linearly modified by a digital word whose bits control whether the elements in the bank are connected or disconnected from the LC-tank. In this structure, therefore, the varactor provides the continuous fine tuning of the LC-VCO whereas the switched capacitor bank provides its coarse tuning with finite frequency steps.
Ideally, the elements of the switched capacitor bank should contribute their nominal capacitance when connected to the LC-tank and a zero capacitance when disconnected. Consequently, if the capacitances are binary scaled, their contribution varies linearly from zero to a maximum value according to the digital control word and therefore the frequency range of the resulting LC-VCO can be extended, doubling it to any desired value, just by adding new binary-scaled capacitors. This is relevant because adding more coarse bands to the frequency tuning range of the oscillator alleviates the fine gain requirements for each band, which improves the reliability of the PLL.
Real LC-VCOs use NMOS switches to connect the capacitors to the LC-tank. To decrease their parasitic resistance and not degrade the Q factor for better phase noise, switch transistors are doubled in size following the tank capacitors. Nevertheless, this has a negative effect in that their OFF parasitic capacitance also increases, thus reducing the overall tuning range. This is analyzed in [3], where it is concluded that increasing the size of the switched capacitor bank beyond 6 elements has no beneficial effect on the tuning of LC-VCOs. According to this result, thus, the number of coarse bands in LC-VCOs is limited to 64, which in turn has an effect on the minimum fine tuning gain achievable and therefore on the operation reliability of the PLL.
Preliminary simulation results reported in [4] showed that acting on the sizing of the transistors in the switches allows overcoming the limit of 6 elements established in [3], therefore achieving increased frequency resolution over a wide tuning range. In particular, [4] shows that increasing the size of the transistors acting as switches in the LC-tank in binary steps results in a narrow capacitance variation for large LC-tanks, whereas a significant increase in the capacitance variation, almost equalling the value expected for ideal parasitic-less switches, with an almost linear capacitance characteristic can be achieved stepping the size increments into fewer levels.
This paper demonstrates experimentally the proposed scheme by two LC-VCOs incorporating a 7-element capacitor bank. The prototypes are fabricated in a reliable and cost-effective 0.18 μm CMOS process, whose feasibility to implement reliable, low-power multi-gigahertz oscillators has already been shown [5]. One of the LC-VCOs (VCO 1) covers a wide 41% tuning range from 1.35 GHz to 2.05 GHz in 128 overlapping bands, allowing a fine tuning gain lower than 40 MHz V− 1. The other one (VCO 2) incorporates the same capacitor bank, thus achieving the same 700 MHz tuning range, from 2.05 GHz to 2.75 GHz, also in 128 overlapping bands; because the frequency of oscillation is higher than in the other prototype, the 700 MHz tuning range translates into 29% with a fine frequency gain lower than 50 MHz V− 1. This feature is imposed by the application for which the LC-VCOs are designed (a frequency synthesizer), which requires equal tuning ranges in absolute value for the two of them, but demonstrates that the proposed scheme is valid to achieve wideband LC-VCOs and that it is scalable and therefore transferable to shorter technologies to achieve higher oscillation frequencies.
The paper is organized as follows: Section 2 elaborates on the coarse tuning of LC-VCOs and introduces the proposed sizing for the switch transistors; Section 3 presents the experimental characterization of the two 7-bit LC-VCOs fabricated with the proposed scheme; and, finally, conclusions are drawn in Section 4.
Section snippets
Coarse tuning in LC-VCOs
In an ideal LC-VCO, the capacitance contributed by the switched capacitor bank is given by the addition of the capacitances of the elements connected to the LC-tank. Since they are binary scaled from a unitary element C1, the total capacitance contributed by an N-element bank varies linearly from zero to Cmax = (2N − 1)C1, which means that the oscillation frequency of the LC-VCO can ideally be extended from a maximum value given by the parasitic capacitance of all the elements in the LC-tank to any
Experimental results
To verify the proposed sizing scheme, two 7-bit LC-VCOs have been fabricated in a standard 0.18 μm CMOS process fed at 1.8 V. The prototypes have been tested on-wafer with a 3-contact DC probe for power supply, an 8-contact DC probe for the 7-bit binary coarse tuning and the analogue fine tuning, and a differential AC probe for the output. Fig. 4 shows a micro-photograph of the fabricated 2.05 GHz to 2.75 GHz LC-VCO along with an indication of its main components, and Fig. 5 displays a close-up of
Conclusions
This paper presents a novel sizing scheme for the switched capacitor bank of LC-VCOs that allows increasing the number of scaled elements in it beyond what can be achieved in traditional binary scaled implementations, which results in a wider tuning range and higher frequency resolution. The proposed scheme is tested by two gigahertz LC-VCOs fabricated in a cost-effective 0.18 μm CMOS process fed at 1.8 V. The fabricated oscillators cover their tuning range in 128 bands, achieving an FOMT
References (9)
- et al.
Power amplifier resilient design for process and temperature variations using an on-chip PLL sensing signal
Microelectron. Reliab.
(2014) - et al.
A 0.18 m CMOS ring VCO for clock and data recovery applications
Microelectron. Reliab.
(2011) - et al.
A 4.39–5.26 GHz LC-tank CMOS voltage-controlled oscillator with small VCO-gain variation
IEEE Microwave Wireless Compon. Lett.
(Aug 2009) - et al.
A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration
IEEE J. Solid State Circuits
(April 2005)
Cited by (12)
A fully integrated nanosecond burst RF generator for quantum technologies
2024, Electronics LettersCMOS High Swing and Q Boosted Dual Core Voltage Controlled Oscillator for 5G New Radio Application
2023, Applied Computational Electromagnetics Society JournalA 0.49 mm<sup>2</sup> CMOS Low-Power TVCO Achieving FoM of 190.36 dBc/Hz for 5G New Radio Application
2022, Elektronika ir ElektrotechnikaDesign of a 10 GHz LC-VCO with low tuning gain fluctuation
2021, Guofang Keji Daxue Xuebao/Journal of National University of Defense TechnologyA reconfigurable radio-frequency converter IC in 0.18 µm CMOS
2019, Electronics (Switzerland)High Performance Oscillator Design Using High-Q Substrate Integrated Waveguide (SIW) Resonator
2019, 2019 6th International Conference on Signal Processing and Integrated Networks, SPIN 2019
- ☆
This work has been supported by MICINN-FEDER under grant TEC2014-52840-R, and FPU fellowship program to J. Aguirre.