Elsevier

Microelectronics Reliability

Volume 65, October 2016, Pages 20-26
Microelectronics Reliability

Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs

https://doi.org/10.1016/j.microrel.2016.07.003Get rights and content

Highlights

  • Proposing an accurate model for RSNM of 6T FinFET SRAM considering SBD and BTI

  • Presenting the study of BTI and SBD combined effects on RSNM of 6T FinFET SRAM

  • The accuracy and speed comparisons of the model to those of Monte Carlo simulation

Abstract

In this paper, an accurate aging model for Read Static Noise Margin (RSNM) of conventional 6 transistors (6T) FinFET SRAM cell is presented. The model, which is developed based on accurate I-V formulation suitable for FinFET, considers soft oxide breakdown (SBD) as well as bias temperature instability (BTI) effects. The accuracy of the model is verified by comparing its results with those of HSPICE simulations for the 14 nm and 10 nm technologies. The results show the maximum errors of 0.63% and 0.54% for the 14 nm and 10 nm technologies, respectively, when averaged over a wide range of stress times and supply voltages. The model also may be used to accurately predict the cumulative distribution function of the RSNM in the presence of the process variation with a very small error compared to the one obtained from the Monte Carlo approach with a considerably short runtime.

Introduction

Reducing supply voltage with scaling has been slowed down due to the reliability problems [1]. On the other hand, the gate dielectric thickness is shrinking with technology developments. As a result, the electric field in the gate oxide dielectric increases as the technology feature size scales down making the gate oxide breakdown as one of the important failure mechanisms in advanced technologies [2]. The failure induces from the trap generation within the oxide as the stress time enlarges causing the gate leakage current increase. This leads to a gradual formation of a conduction path in the gate oxide (soft oxide breakdown) [3]. In addition, the gate voltage control on device current flow between the drain and source deteriorates affecting reliability and functionality of the circuit. Strong electric fields can also cause other temporal variabilities such as bias temperature instability (BTI) which occurs when the transistor is under stress [4]. The effect which may be related to the interface- and bulk-trap generation in the oxide layer, causes a shift in the threshold voltage and reduction in the drive current slowing down the device and reducing the reliability. In summary, the BTI appears as a drift of the threshold voltage of the transistors over time while the soft breakdown (SBD) occurs when enough traps are aligned in the gate dielectric such that a conducting path inducing a gate leakage current is created.

Many research efforts have been devoted to investigate these wearout effects [5], [6], [7], [8], [9], [10], [11], [12], [13]. The physics and statistics of the SBD effect have been studied in [5], [6]. The correlation of the NBTI and SBD effects on the performance of digital circuits has been investigated in [7]. The results presented in this work show that the correlation of these effects accelerates the performance deterioration of digital circuits. In some other works, the effects of the SBD ([8], [9], [10]) and BTI [11], [12], [13] on the SRAM cell characteristics have been studied. The studies demonstrate that the most important parameter of SRAM cells degrading with these effects is the read stability. In [14], [15], the SRAM cell read stability considering both SBD and BTI for conventional bulk MOSFET was studied through suggested analytical models. For advanced technologies (sub 32-nm nodes), the transistor structure has migrated from the conventional bulk to the FinFET device for a better short channel effects control [1], [16]. Hence, the study of the wearout in conjunction with the process variation effects of these devices on the circuit stability is required. As the simulations for this study are typically very time consuming, analytical models which provide quick insightful results are worth developing.

In this paper, we present an accurate aging model for Read Static Noise Margin (RSNM) of conventional 6 transistors (6T) FinFET SRAM cell. More specifically, the contributions of the paper are summarized below:

  • A model is presented for the RSNM of FinFET SRAM considering the SBD and BTI effects based on an accurate I-V model suitable for nanoscale FinFET. The model has a good accuracy for a wide range of supply voltages for 14 nm and 10 nm technologies.

  • For predicting the SBD and BTI effects, appropriate models with calibrated parameters for FinFET are exploited. Then, the combined effects of the BTI and SBD on the RSNM degradation of the FinFET SRAM are studied. The proposed model follow the simulation results very well, too.

  • It is demonstrated that the proposed RSNM model keeps its accuracy under process variations and is capable of accurately modeling the statistical distributions of RSNM over its life-time.

The rest of this paper is organized as follows. In Section 2, I-V and aging characteristics models are presented. The RSNM model considering the SBD and BTI effects for the FinFET SRAM is presented in Section 3 while the results are discussed in Section 4. Finally, Section 5 concludes the paper.

Section snippets

I-V characteristic

For obtaining analytical expression for the RSNM, the I-V model should be simple. On the other hand, since we are considering highly scaled FinFET technologies, the model should have sufficient accuracy. In this work, the analytical expressions of the model presented in [17] are adopted to satisfy both simplicity and accuracy. The model may be utilized for nanoscale transistors with channel lengths down to 5 nm with enough accuracy. The current expressions of the model for both the saturation

RSNM modeling considering the SBD effect

For measuring the static noise margin, two DC noise voltage sources (Vn) with the worst-case polarity are applied at the internal nodes of the cell as shown in Fig. 2. Here, we consider the case of storing “0” at the right storage node (R) for a long time (DC stress) as a worst-case scenario for the aging effects. The SNM is the maximum amount of noise voltage that can be applied at the storage nodes such that the stored value of the cell is not changed. Different equivalent criteria for the

Results and discussion

To assess the accuracy of the proposed model, we have compared the RSNM values of the 6 T SRAM cell obtained through HSPICE simulations with those of the model for the 14 nm and 10 nm FinFET technologies [18]. First, the RSNM versus RSBD for the nominal VT as well as with 5% and 10% VT shifts for both the transistors PL and NR are plotted in Fig. 4. As the figure reveals, the model has a very good accuracy for a wide range of RSBD and the threshold voltage shifts considered here.

As shown in [14],

Conclusion

In this work, an analytical aging model for the RSNM of the FinFET based SRAM considering the SBD and BTI effects was presented. The model was developed based on an I-V model suitable for the FinFET. The accuracy of the model was verified by comparing its prediction against HSPICE simulations for the 14 nm and 10 nm FinFET technologies. The results verified a high accuracy for the model for a wide range of supply voltages and stress times. Also, the predictions of the model in the presence of the

Acknowledgements

BE and AAK acknowledge the financial support by the Iranian National Science Foundation (INSF).

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