Investigation of temperature variations on analog/RF and linearity performance of stacked gate GEWE-SiNW MOSFET for improved device reliability
Introduction
CMOS devices are extensively used in the field of satellite communications, military, medical equipment, automobile, nuclear sectors, and wireless/mobile communications. For these applications and the demand of nanoscale transistor, it is important to investigate the device behavior at a wide range of temperatures [1]. Also, it has been demonstrated that the performance of MOS devices significantly improves when operating at low temperatures in terms of improved carrier mobilities, on-currents, gain, sub-threshold slope, cut-off frequency, short-channel effects and noise performance [2], [3]. The unwanted flow of high leakage current through the junction and the presence of latch-up put a limit on the use of bulk MOS devices at high temperatures. Several technologies have been reported in the literature as an option for both low and high-temperature operations. Some of them are Silicon on Insulator (SOI) [4], Recessed Channel [5], III–V semiconductors [6], Nanowire transistors [7], etc. Among them, SiNW emerged as most favorable in electronic devices due to the fact that its concentration, dopant type can be changed during synthesis. Also, its mobility is higher than bulk silicon due to stronger 1D quantum confinement. The body thickness of the nanowire can readily be reduced to a few nm in size that is the major challenge to achieve using bulk silicon. Also, since hot carrier degradation is a major concern for short channel MOSFETs [8], several engineering schemes are reported in literature such as gate metal workfunction engineering [9], drain engineering and channel engineering to overcome this degradation. Moreover, the high-k gate dielectric is required for suppressing the leakage current with scaling of gate oxide. The high-k gate stack also improves Short Channel Effects (SCEs) and increases Ion/Ioff ratio in sub-100 nm regime. Therefore, a novel device is proposed in which stacked gate architecture is implemented on Gate Electrode Workfunction Engineered (GEWE) Silicon Nanowire MOSFET. In this work, for the first time performance and reliability issues of SG-GEWE-SiNW MOSFET are examined in terms of Analog, RF/Noise and Linearity FOMs at different temperatures (200–600 K) with an aim to analyze the temperature at which the device is more reliable for analog and RF applications. The results so obtained are simultaneously compared with GEWE-SiNW and SiNW MOSFET. Section 2 explains the 2D cross-sectional view of three different device structures including all the necessary boundary conditions. In Section 3, all the default simulation models are described along with the calibration of simulation models with experimental results. Section 4 contains the results obtained by device variation at 200–600 K and conclusions are drawn in Section 5.
Section snippets
Device structure and its description
Fig. 1(a) shows the simulated 3-D device structure of SG-GEWE-SiNW MOSFET and its 2-D cross-sectional view along with GEWE-SiNW and SiNW MOSFET are shown in Fig. 1(b–c). The detailed descriptions of all the three device structures are listed in Table 1. All simulations have been performed using ATLAS and DEVEDIT 3D device simulator.
With GEWE (workfunction transition) scheme, there is a significant reduction in the SCEs, current driving capability improves due to step potential which is due to
Simulation methodology
All simulations have been performed using the ATLAS device simulator [13]. The physical models used during simulations are shown in Table 3. Moreover, the quantum confinement in the sub-nm scaled device may not be negligible [14] because the inversion layer thickness in the conducting silicon nanowire channel is comparable to the nanowire dimension. Thus, the quantization effect is also taken care of in the simulation. To incorporate all non-local effects, we have adopted the quantum mechanical
Analog performance
In this sub-section, the analog performance of all three device structures is studied under different temperatures (200 K–600 K) with an aim to analyze the reliability issues in terms of analog FOMs such as on-current, device efficiency, switching ratio, Subthreshold swing (SS) and Threshold Voltage (Vth). Fig. 3(a) shows the transfer characteristics of SiNW, GEWE-SiNW and GS-GEWE-SiNW MOSFET for different temperatures. With the increase in temperature, the drain current rises but at a particular
Conclusion
The effect of temperature on the Analog/RF and Linearity performance has been studied with an aim to analyze the reliability issues of SG-GEWE-SiNW. Results reveal that with the incorporation of Stack Gate scheme, device performance enhances significantly due to reduction in leakage current. SG-GEWE-SiNW MOSFET exhibits 1.1 and 1.2 times improvement in Ion and thus 29% and 9.3% enhancement in fT at low temperature (200 K) in comparison to GEWE-SiNW and SiNW MOSFET owing to decrement in
Acknowledgment
The authors would like to thank the Microelectronics Research Lab, Department of Engineering Physics, Delhi Technological University (formerly DCE) and one of the authors (Neha Gupta) is grateful to the University Grant Commission (UGC) (Ref.: 4003/NET-June 2013) for providing the necessary financial assistance to carry out this research work.
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