Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop
Introduction
With the scaling down in technology nodes, microelectronic devices benefit from a decrease in operating voltage and an increase in frequency. This however poses a challenge to the community involved in high-reliability systems as reliability margins get thinner and major concerns arise on the long-term viability of integrated circuits. On top of these reliability concerns, electronics used in space applications face additional source of degradation from radiation damage [1]. The conventional qualification standards subject electronic devices to reliability and radiation tests, separately. As device features shrink, reliability degradation could affect radiation performance and thus, is worthy to investigate upon.
Recently, there has been an increase in studies focused on the interactions between traditional reliability issues such as time dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) [2] and radiation damages such as total ionizing dose (TID) [3] and single event effects (SEE) [4].
In 2008, Cannon and co-workers [5] reported their work on the effects of aging on 65 nm silicon-on-insulator SRAM soft error rates. In their study, electrical parameter shifts due to TDDB and NBTI have been modeled and results indicated that aging can either increase or decrease the device critical charge (Qcrit), depending on the site of breakdown. However, upon consideration of experimental uncertainty, the study ultimately concluded that aging does not have a significant effect on the soft error rates of an SRAM. In another study, Moukhtari and colleagues [6] found a decrease in single event transient (SET) sensitivity after NBTI stress on a 65 nm bulk CMOS test vehicle. In their study, various chains of inverters, NOR gates and flip flops were investigated and showed a decrease in SET sensitivity. Kauppila and co-workers [7] showed an increase in cross-section of single event upset (SEU) after 12 h of NBTI stress on 40 nm bulk flip flop. These conflicting results form the basis of this presented work and the authors endeavor to provide more evidence in this field. It is the authors' opinion that in some cases, difference in results may be due to difference in technology and design of the tested devices' structures. For example, silicon-on-insulator devices have a minimal oxide layer with good isolation between source/drain. Thus, electrical parameter shifts due to aging could be mild and ultimately lead to limited effects on radiation response. Also, different stress conditions (using both voltage and temperature) may complicate the extent of aging stress on the device and make comparisons between studies difficult.
In this paper, investigation on the effects of solely voltage stress on the SEU response of a chain of flip flops was conducted. SEU was induced by a newly integrated laser system (more details in Section 2.2) and captured by an oscilloscope. These SEU occurrences were then superimposed with the device micrograph to obtain laser mappings, allowing us to localize sensitive regions within the device architecture. This paper presents new evidence to support the hypothesis that voltage stress affects the SEU response of flip flop chains fabricated in advanced bulk CMOS technology. In addition, comparisons between cross-section versus laser energy curves were conducted in order to evaluate the change in SEU sensitivity after various durations of voltage stress.
Section snippets
Test structure description and voltage stress condition
The test structures used in this work were chains of 100 flip flops (as shown in Fig. 1a) manufactured in the 65 nm low power bulk CMOS process technology by Global Foundries. The nominal operating voltage for such a process is 1.2 V.
As illustrated in Fig. 1b, each flip flop is fundamentally made of inverters with pass gates controlled by the clock signal. The flip flop chains were dispersed among other designs in order to mimic the randomized layout in real applications. Parts were opened on the
Laser SET mapping and cross-section versus laser energy curve
The laser SEU mappings of a fresh sample are shown in Fig. 2. As expected, it can be observed that the area of SEU sensitive regions (in red) increased with laser energy. Also, the sensitive area at low laser energy remained sensitive at high laser energy. This process was repeated at various time points of voltage stress to evaluate the SEU sensitivity of the sample and these results are illustrated in Fig. 3. As the duration of voltage stress increases, the sensitive area also increases. The
Simulation on electrical parameter variation and SEU response of test structure
Electrical circuit simulations (via Cadence Spectre) were conducted to better understand the fundamental changes in electrical parameter and SEU response of the test structure. A single inverter was chosen as the test subject as this is the fundamental building block of a flip flop. The inverter was supplied with a Vdd of 0.9 V and input was held LOW during the simulation. The drain current is a function of the threshold voltage, Vth, which has also been shown in several studies [11], [12], [13]
Conclusion
In the presented work, voltage stress on 65 nm flip flop chains has been shown to increase the SEU sensitivity of such structures. SEU was studied using a newly integrated pulsed laser system with test structure being stressed at 12.5% above the nominal voltage and up to a maximum duration of 130 h. This increase in SEU sensitivity was found to be related to electrical parameter variations and SPICE simulations were conducted to gain a better understanding of the observed trends.
Acknowledgments
The authors are grateful for the helpful discussions with several people, with particular mention of Samuel Chef for advices on Matlab processing, Juanda and Lin Tong for advices on SPICE simulations. The first author is thankful to CNES for offering a conducive laboratory environment for discussions and experimental work. This work is also supported by the PHC Merlion Ph.D Program.
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